- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377740 > LTC1294CIJ (LINEAR TECHNOLOGY CORP) Single Chip 12-Bit Data Acquisition System PDF資料下載
參數(shù)資料
| 型號： | LTC1294CIJ |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Single Chip 12-Bit Data Acquisition System |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 494K |
| 代理商： | LTC1294CIJ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
21
LTC1293/LTC1294/LTC1296
Usually V
ERROR
will not be significant. For a 60Hz signal
on the “–” input to generate a 0.25LSB error (300
μ
V) with
the converter running at CLK = 1MHz, its peak value would
have to be 66mV. Rearranging the above equation the
maximum sinusoidal signal that can be digitized to a given
accuracy is given as:
f
V
V
f
MAX
ERROR MAX
π
2
PEAK
CLK
12
(–)
(
)
=
For 0.25LSB error (300
μ
V) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Unused inputs should be tied to the ground plane.
Reference Input
The voltage on the reference input of the LTC1293/4/6
determines the voltage span of the A/D converter. The
reference input has transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 12). During each bit test of the conversion
(every CLK cycle) a capacitive current spike will be gener-
ated on the reference pin by the A/D. These current spikes
settle quickly and do not cause a problem. If slow settling
circuitry is used to drive the reference input, take care to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
U
S
A
O
PPLICATI
IU
U
Figure 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time for
the reference to settle. Even at the maximum CLK rate of
1MHz most references and op amps can be made to settle
within the 1
μ
s bit time. For example the LT1027 will settle
adequately or with a 10
μ
F bypass capacitor at V
REF
the
LT1021 also can be used.
V
V
Figure 14. Poor Reference Settling Can Cause A/D Errors
HORIZONTAL: 1
μ
s/DIV
HORIZONTAL: 1
μ
s/DIV
Figure 13. Adequate Reference Settling (LT1027)
Figure 12. Reference Input Equivalent Circuit
R
ON
8pF – 40pF
LTC1293/4/6
REF+
14
R
OUT
V
REF
EVERY CLK CYCLE
13
REF–
LTC 1293 F12
Reduced Reference Operation
The effective resolution of the LTC1293/4/6 can be in-
creased by reducing the input span of the converter. The
LTC1293/4/6 exhibits good linearity over a range of refer-
ence voltages (see typical performance characteristics
curves of Change in Linearity vs Reference Voltage and
Change in Gain Error vs Reference Voltage). Care must be
taken when operating at low values of V
REF
because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. Offset and Noise are
factors that must be considered when operating at low
V
REF
values. For the LTC1293 REF
–
has been tied to the
AGND pin. Any voltage drop from the AGND pin to the
ground plane will cause a gain error.
Offset with Reduced V
REF
The offset of the LTC1293/4/6 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical performance characteris-
tic curve of Unadjusted Offset Error vs Reference Voltage
shows how offset in LSB’s is related to reference voltage
for a typical value of V
OS
. For example a V
OS
of 0.1mV,
which is 0.1LSB with a 5V reference becomes 0.4LSB with
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1296DC | Single Chip 12-Bit Data Acquisition System |
| LTC1296DCN | Single Chip 12-Bit Data Acquisition System |
| LTC1296DCS | Single Chip 12-Bit Data Acquisition System |
| LTC1294CC | Single Chip 12-Bit Data Acquisition System |
| LTC1294CCN | Single Chip 12-Bit Data Acquisition System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1294DCJ | 制造商:Linear Technology 功能描述:ADC Single SAR 46.5ksps 12-bit Serial 20-Pin CDIP |
| LTC1294DCN | 功能描述:IC DATA ACQ SYSTEM 12BIT 20-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| LTC1294DCN#PBF | 功能描述:IC DATA ACQ SYST 12-BIT 20DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Data Converter Basics 標準包裝:1 系列:- 類型:電機控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應商設備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| LTC1294DCSW | 功能描述:IC DATA ACQ SYSTEM 12BIT 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| LTC1294DCSW#PBF | 功能描述:IC DATA ACQ SYSTEM 12BIT 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Data Converter Basics 標準包裝:1 系列:- 類型:電機控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應商設備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。