參數(shù)資料
型號: LTC1296CISW#PBF
廠商: Linear Technology
文件頁數(shù): 10/28頁
文件大小: 0K
描述: IC DATA ACQ SYSTEM 12BIT 20-SOIC
標準包裝: 38
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 12 b
采樣率(每秒): 46.5k
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 雙 ±
電源電壓: ±5V,5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC
包裝: 管件
18
LTC1293/LTC1294/LTC1296
129346fs
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
LTC1294. Figure 4 shows an example of an ideal LTC1293/
4/6 ground plane design for a two sided board. Of course
this much ground plane will not always be possible, but
users should strive to get as close to this ideal as possible.
Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
ground during a conversion cycle can induce errors or
noise in the output code. VCC noise and ripple can be kept
below 0.5mV by bypassing the VCC pin directly to the
analog ground plane with a minimum of 22
F tantalum
capacitor and with leads as short as possible. The lead
from the device to the VCC supply also should be kept to a
minimum and the VCC supply should have a low output
impedance such as obtained from a voltage regulator
(e.g., LT323A). For high frequency bypassing a 0.1
F
ceramic disk placed in parallel with the 22
F is recom-
mended. Again the leads should be kept to a minimum.
Figure 5 and 6 show the effects of good and poor VCC
bypassing.
HORIZONTAL: 10
s/DIV
VERTICAL:
0.5mV/DIV
VERTICAL:
0.5mV/DIV
HORIZONTAL: 10
s/DIV
Figure 5. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors.
Figure 6. Good VCC Bypassing Keeps Noise
and Ripple on VCC Below 1mV
CS
VCC
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1293/4/6
have capacitive switching input current spikes. These
current spikes settle quickly and do not cause a problem.
If large source resistances are used or if slow settling op
amps drive the inputs, take care to insure the transients
caused by the current spikes settle completely before the
conversion begins.
Figure 4. Ground Plane for the LTC1293/4/6
Figure 7. Analog Input Equivalent Circuit
6TH CLK
RON = 500
8TH CLK
CIN =
100pF
LTC1293/4/6
“+”
INPUT
RSOURCE +
VIN +
C1
“–”
INPUT
RSOURCE
VIN
C2
LTC1293 F07
V
22
F
TANTALUM
VCC
LTC1293 F04
0.1
F
CERAMIC
DISK
ANALOG
GROUND
PLANE
0.1
F
CERAMIC
1
2
3
4
5
6
7
8
9
10
20
19
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