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參數(shù)資料
| 型號： | LTC1297CCN8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA ACQ SYSTEM 12BIT 8-DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 60k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 單電源 |
| 電源電壓： | 5V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
14
LTC1292/LTC1297
12927fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Source Resistance
The analog inputs of the LTC1292/LTC1297 look like a
100pF capacitor (CIN) in series with a 500 resistor (RON)
(Figures 10a and 10b). CIN gets switched between (+) and
(–) inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constant is short enough to allow the analog inputs to
settle completely within the allowed time.
“+” Input Settling
The input capacitor for the LTC1292 is switched onto the
“+” input during the sample phase (tSMPL, see Figures 11a,
11b and 11c). The sample period can be as short as tWHCS
+ 1/2 CLK cycle or as long as tWHCS + 1 1/2 CLK cycles
before a conversion starts. This variability depends on
where CS falls relative to CLK. The voltage on the “+” input
must settle completely within the sample period. Minimizing
RSOURCE+ and C1 will improve the settling time. If large “+”
input source resistance must be used, the sample time can
be increased by using a slower CLK frequency. With the
minimum possible sample time of 3.0
s, RSOURCE+ < 2.0k
and C1 < 20pF will provide adequate settling time.
The sample period for the LTC1297 starts on the falling
edge of CS and ends on the falling edge of the first CLK
Figure 11a. Setup Time (tsuCS) Is Met for the LTC1292
“+” and “–” Input Settling Windows
(Figure 12). The length of the sample period is tsuCS +0.5
CLK cycles. Again, the voltage on the “+” input must settle
completely within the sample period. If large “+” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency or by increasing
Figure 10a. Analog Input Equivalent Circuit for the LTC1292
Figure 10b. Analog Input Equivalent Circuit for the LTC1297
CS
↑ R
ON
500
tWHCS
+ 0.5 CLK
CIN
100pF
LTC1292
“+”
INPUT
RSOURCE +
VIN +
C1
“–”
INPUT
RSOURCE –
VIN –
C2
LTC1292/7 F10a
CS
↓ R
ON
500
tsuCS
+ 0.5 CLK
CIN
100pF
LTC1297
“+”
INPUT
RSOURCE +
VIN +
C1
“–”
INPUT
RSOURCE –
VIN –
C2
LTC1292/7 F10b
DOUT
CLK
B11
HI-Z
B9
B10
LTC1292/7 F11a
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
tSUCS
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
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