TYPICAL APPLICATIONS N U Interfacing t" />
參數(shù)資料
型號(hào): LTC1298IS8#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 15/24頁(yè)
文件大?。?/td> 0K
描述: IC A/D CONV SAMPLING 12BIT 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 11.1k
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.8mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極
22
LTC1286/LTC1298
TYPICAL APPLICATIONS N
U
Interfacing to the Parallel Port of the INTEL 8051
Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1298 and parallel port micro-
processors. Normally the CS, CLK and DIN signals would
be generated on 3 port lines and the DOUT signal read on
a 4th port line. This works very well. However, we will
demonstrate here an interface with the DIN and DOUT of the
LTC1298 tied together as described in the SERIAL INTER-
FACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1298 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
LABEL
MNEMONIC
OPERAND
COMMENTS
MOV
A, #FFH
DIN word for LTC1298
SETB
P1.4
Make sure CS is high
CLR
P1.4
CS goes low
MOV
R4, #04
Load counter
LOOP 1
RLC
A
Rotate DIN bit into Carry
CLR
P1.3
SCLK goes low
MOV
P1.2, C
Output DIN bit to LTC1298
SETB
P1.3
SCLK goes high
DJNZ
R4, LOOP 1
Next bit
MOV
P1, #04
Bit 2 becomes an input
CLR
P1.3
SCLK goes low
MOV
R4, #09
Load counter
LOOP 2
MOV
C, P1.2
Read data bit into Carry
RLC
A
Rotate data bit into Acc.
SETB
P1.3
SCLK goes high
CLR
P1.3
SCLK goes low
DJNZ
R4, LOOP 2
Next bit
MOV
R2, A
Store MSBs in R2
CLR
A
Clear Acc.
MOV
R4, #04
Load counter
LOOP 3
MOV
C, P1.2
Read data bit into Carry
RLC
A
Rotate data bit into Acc.
SETB
P1.3
SCLK goes high
CLR
P1.3
SCLK goes low
DJNZ
R4, LOOP 3
Next bit
MOV
R4, #04
Load counter
LOOP 4
RRC
A
Rotate right into Acc.
DJNZ
R4, LOOP 4
Next Rotate
MOV
R3, A
Store LSBs in R3
SETB
P1.4
CS goes high
DOUT FROM 1298 STORED IN 8501 RAM
MSB
R2
B11 B10 B9
B8 B7 B6 B5 B4
LSB
R3
B3
B2
B1 B0 0
0
CS
CLK
DOUT
DIN
LTC1298
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
LTC1286/98 TA01
CLK
MSBF BIT LATCHED
INTO LTC1298
8051 P1.2 OUTPUTS DATA
TO LTC1298
LTC1298 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1298 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
8051 P1.2 RECONFIGURED
AS IN INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
MSBF
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SGL/
DIFF
START
DATA
(DIN/DOUT)
LTC1286/98 TA02
CS
ODD/
SIGN
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