參數(shù)資料
型號(hào)： LTC1343CGW#TR
廠商： Linear Technology
文件頁數(shù)： 9/28頁
文件大?。?/td> 0K
描述： IC TXRX SOFTWARE SELECT 44SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： 多協(xié)議
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-BSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 44-SSOP
包裝： 帶卷 (TR)
17
LTC1343
No-Cable Mode
The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedance state, and the supply current drops to less than
200
A. It can also be used to share I/O lines with other
drivers and receivers without loading down the signals.
Charge Pump
The LTC1343 uses an internal capacitive charge pump to
generate VDD and VEE as shown in Figure 28. A voltage
doubler generates about 8V on VDD and a voltage inverter
generates about – 7.5V for VEE. Four 1F surface mounted
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The VEE capacitor C5 should be a minimum of
3.3
F. All capacitors are 16V.
Receiver Fail-Safe and Glitch Filter
All LTC1343 receivers feature fail-safe operation in all
modes except no-cable mode. If the receiver inputs are left
floating or shorted together by a termination resistor, the
receiver output will always be forced to a logic high.
External pull-up resistors are required on receiver outputs
if fail-safe operation in the no-cable mode is desired.
When the chip is configured for control signals by pulling
the CTRL/CLK pin high, a glitch filter is connected to all
receiver inputs. The filter will reject any glitches at the
receiver inputs less than 300ns.
V.10 Driver Rise and Fall Times
The rise and fall times of the V.10 drivers is programmed
by placing a 1/8W, 5% resistor between the 423 SET (Pin
25) and ground. The graph of Driver Rise and Fall Times
vs Resistor Value is shown in Figure 29.
Enabling the Single-Ended Driver and Receiver
When the LTC1343 is being used to generate the control
signals (CTRL/CLK = high) and the EC pin is pulled low, the
DCE/DTE pin becomes an enable for driver 1 and receiver
4 so their inputs and outputs can be tied together as shown
in Figure 30.
APPLICATIONS INFORMATION
WU
U
Figure 30. Single-Ended Driver and Receiver Enable
Figure 29. V.10 Driver Rise and Fall Time vs Resistor Value
Figure 28. Charge Pump
44
43
42
41
40
1343 F28
1
2
3
4
8
C3
1
F
C4
1
F
5V
C1
1
F
C2
1
F
C5
3.3
F
LTC1343
VDD
C1+
PWRVCC
C1–
VCC
C2+
C2–
VEE
PGND
GND
+
RESISTANCE (
)
DRIVER
RISE/FALL
TIME
(
s)
1k
100
10
1
0.1
100k
1M
5M
1343 F29
10k
39
26
LTC1343
1343 F30
5
21
16
20
24
EC
D1
CTRL/CLK
DCE/DTE
R4
VCC
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