參數(shù)資料
型號: LTC1350C
廠商: Linear Technology Corporation
英文描述: Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-PDIP 0 to 70
中文描述: 3.3V低功耗EIA/TIA-562 3驅動器/ 5接收器
文件頁數(shù): 5/8頁
文件大?。?/td> 219K
代理商: LTC1350C
5
LTC1350
PI FU
V
CC
:
3.3V Input Supply Pin. Supply current is typically
35
μ
A in the SHUTDOWN mode. This pin should be de-
coupled with a 0.1
μ
F ceramic capacitor.
GND:
Ground Pin.
ON/OFF:
TTL/CMOS Compatible Shutdown Pin. A logic
low puts the device in the SHUTDOWN mode with receiv-
ers 4 and 5 kept alive and the supply current equal to 35
μ
A.
All driver and other receiver outputs are in high impedance
state. This pin cannot float.
V
+
:
Positive Supply Output. V
+
2V
CC
– 1V. This pin
requires an external capacitor (C = 0.1
μ
F) for charge
storage. The capacitor may be tied to ground or V
CC
. With
multiple devices, the V
+
and V
pins may be paralleled into
common capacitors. For a large number of devices, in-
creasing the size of the shared common storage capaci-
tors is recommended to reduce ripple.
V
:
Negative Supply Output. V
–(2V
CC
– 1.3V). This
pin requires an external capacitor (C = 0.1
μ
F) for charge
storage.
U
SWITCHU
W
1.4V
0V
V
CC
0V
V
+
V
0V
DR
INPUT
DR
OUTPUT
1.4V
HLD
LHD
LTC1350 F01
0.8V
V
CC
0V
2.4V
RX
INPUT
RX
OUTPUT
1.3V
HLR
1.7V
LHR
LTC1350 F02
V
CC
0V
Figure 2. Receiver Propagation Delay Timing
Figure 1. Driver Propagation Delay Timing
C1
+
, C1
, C2
+
, C2
:
Commutating Capacitor Inputs. These
pins require two external capacitors (C = 0.1
μ
F): one from
C1
+
to C1
and another from C2
+
to C2
. To maintain
charge pump efficiency, the capacitor’s effective series
resistance should be less than 20
.
DR IN:
EIA/TIA-562 Driver Input Pins. Inputs are TTL/
CMOS compatible. Inputs should not be allowed to float.
Tie unused inputs to V
CC
.
DR OUT:
Driver Outputs at EIA/TIA-562 Voltage Levels.
Outputs are in a high impedance state when in the SHUT-
DOWN mode or V
CC
= 0V. The driver outputs are protected
against ESD to
±
10kV for human body model discharges.
RX IN:
Receiver Inputs. These pins can be forced to
±
25V
without damage. The receiver inputs are protected against
ESD to
±
10kV for human body model discharges. Each
receiver provides 0.4V of hysteresis for noise immunity.
RX OUT:
Receiver Outputs with TTL/CMOS Voltage Lev-
els. Receiver 1, 2 and 3 outputs are in a high impedance
state when in SHUTDOWN mode to allow data line sharing.
Receivers 4 and 5 are kept alive in SHUTDOWN.
相關PDF資料
PDF描述
LTC1350CG Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-SO 0 to 70
LTC1350CN Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-SO 0 to 70
LTC1350CS Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-SO 0 to 70
LTC1350I 3.3V Low Power EIA/TIA-562 3-Driver/ 5-Receiver Transceiver
LTC1350 3.3V Low Power EIA/TIA-562 3-Driver/ 5-Receiver Transceiver(3.3V,低功率,EIA/TIA-562,3發(fā)5收收發(fā)器)
相關代理商/技術參數(shù)
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