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參數(shù)資料
| 型號： | LTC1380IS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Single-Ended 8-Channel/ Differential 4-Channel Analog Multiplexer with SMBus Interface |
| 中文描述： | 8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SO-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 275K |
| 代理商： | LTC1380IS |
9
LTC1380/LTC1393
APPLICATIO
S I
FOR
ATIO
U
Table 1. LTC1380/LTC1393 Address Selection
A1
A0
0
0
0
1
1
0
1
1
W
U
U
LTC1380
90H
92H
94H
96H
LTC1393
98H
9AH
9CH
9EH
SCL is the synchronizing clock generated by the host. SDA
is the bidirectional data transfer between the host and the
slave. The host initiates a start bit by dropping the SDA line
from High to Low while the SCL is High. The stop bit is
initiated by changing the SDA line from Low to High while
SCL is High. All address, command and acknowledge
signals must be valid and should not change while SCL is
High. The acknowledge bit signals to the host the accep-
tance of a correct address byte or the command byte.
At V
CC
supply above 2.7V, the SCL and SDA input thresh-
old is typically 1V with an input hysteresis of 100mV. The
typical SCL and SDA lines have either a resistive or current
source pull-up at the host. The LTC1380/LTC1393 have an
open-drain NMOS transistor at the SDA pin to sink 3mA
below 0.4V during the slave acknowledge sequence. The
address selection input A1 and A0 are TTL compatible at
V
CC
= 5V.
Both the LTC1380 and LTC1393 are compatible with the
Philips/Signetics I
2
C Bus interface. This 1V threshold for
SCA and SDA should not pose an operational problem
with I
2
C applications.
The multiplexer switches are selected as shown in Table 2.
Both the LTC1380 and the LTC1393 have an enable bit
(EN). A Low disables all switches while a High enables the
selected switch as programmed by bits C2, C1 and C0. A
stop bit after a successful send byte sequence for LTC1380/
LTC1393 will disable all switches before the new selected
switch is connected.
Table 2. Multiplexer Control Bits Truth Table
LTC1380 D
O
CHANNEL STATUS
All Off
S0
S1
S2
S3
S4
S5
S6
S7
LTC1393 D
O+
, D
O–
CHANNEL STATUS
All Off
S0
+
, S0
–
EN
0
1
1
1
1
1
1
1
1
C2
X
0
0
0
0
1
1
1
1
C1
X
0
0
1
1
0
0
1
1
C0
X
0
1
0
1
0
1
0
1
S1
+
, S1
–
S2
+
, S2
–
S3
+
, S3
–
TYPICAL APPLICATIO
N
S
Simplified LTC1393 Application
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1393
S2
+
S2
–
S3
+
S3
–
0.1
μ
F
15k
4 DIFFERENTIAL
ANALOG INPUTS
15k
5V
DIFFERENTIAL
ANALOG OUTPUTS
1380/93 TA03
S0
+
S0
–
S1
+
S1
–
V
CC
SCL
SDA
A0
A1
GND
D
O–
D
O+
SMBus
HOST
SCL
SDA
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