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參數(shù)資料
| 型號： | LTC1400 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Complete SO-8, 12-Bit,400ksps ADC with Shutdown(SO-8封裝，12位,400ksps，模數(shù)轉(zhuǎn)換器（帶關(guān)斷）) |
| 中文描述： | 完整的SO - 8，12位，以其400 kSPS ADC的與關(guān)斷（以SO - 8封裝，12位，以其400 kSPS，模數(shù)轉(zhuǎn)換器（帶關(guān)斷）） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 463K |
| 代理商： | LTC1400 |
13
LTC1400
APPLICATIO
S I
FOR
ATIO
U
350ns. In the Sleep mode, power consumption is reduced
to a minimum by cutting off the supply to all internal
circuitry including the reference. Figure 12 shows the
ways to power down the LTC1400. The chip can enter the
Nap mode by keeping the CLK signal low and pulsing the
CONV signal twice. For Sleep mode operation, CONV
signal should be activated four times while CLK is kept low.
The LTC1400 can be returned to active mode easily. The
rising edge of CLK will wake-up the LTC1400. During the
transition from Sleep mode to active mode, the V
REF
voltage ramp-up time is a function of the loading condi-
tions. With a 10
μ
F bypass capacitor, the wake-up time
from Sleep mode is typically 4ms. A REFRDY signal will be
activated once the reference has settled and is ready for an
A/D conversion. This REFRDY bit is output to the D
OUT
pin
before the rest of the A/D converted code.
W
U
U
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D
OUT
output provides
the conversion result in serial form.
Figure 13 shows the digital timing diagram of the LTC1400
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t
2,
the digital output will be
delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. D
OUT
data should be captured by the receiving
system on the rising CLK edge. Data remains valid for a
minimum time of t
10
after the rising CLK edge to allow
capture to occur.
CLK
CONV
INTERNAL
S/H STATUS
D
OUT
t
7
t
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
t
2
t
6
t
4
t
5
t
8
t
ACQ
SAMPLE
SAMPLE
HOLD
HOLD
Hi-Z
Hi-Z
t
CONV
t
SAMPLE
LTC1400 F13
REFRDY
D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
REFRDY
Figure 13. ADC Digital Timing Diagram
Figure 14. CLK to D
OUT
Delay
t
10
t
8
V
IH
V
OH
V
OL
D
OUT
CLK
t
9
V
IH
90%
10%
D
OUT
CLK
LTC1400 F14
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| LTC1400CS8PBF | 制造商:Linear Technology 功能描述:LTC1400CS8PBF |
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