參數(shù)資料
型號: LTC1400I
廠商: Linear Technology Corporation
英文描述: Complete SO-8, 12-Bit, 400ksps ADC with Shutdown
中文描述: 完整的SO - 8,12位,以其400 kSPS ADC的帶有關(guān)斷
文件頁數(shù): 7/20頁
文件大?。?/td> 515K
代理商: LTC1400I
7
LTC1400
APPLICATIO
S I
N
FOR
ATIO
U
Conversion Details
The LTC1400 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output based on a precision
internal reference. The control logic provides easy inter-
face to microprocessors and DSPs through 3-wire con-
nections.
A rising edge on the CONV input starts a conversion. At the
start of a conversion the successive approximation regis-
ter (SAR) is reset. Once a conversion cycle has begun it
cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
input connects to the sample-and-hold
capacitor during the acquired phase and the comparator
offset is nulled by the feedback switch. In this acquire
phase, it typically takes 200ns for the sample-and-hold
capacitor to acquire the analog signal. During the convert
phase, the comparator feedback switch opens, putting the
comparator into the compare mode. The input switches
connect C
SAMPLE
to ground, injecting the analog input
charge onto the summing junction. This input charge is
successively compared with the binary-weighted charges
supplied by the capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
DAC output balances the A
IN
input charge. The SAR
contents (a 12-bit data word) which represent the input
voltage, are output through the serial pin D
OUT
.
W
U
Dynamic Performance
The LTC1400 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2a shows a
typical LTC1400 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from DC to half the sampling frequency.
Figure 2a shows a typical spectral content with a 400kHz
sampling rate and a 100kHz input. The dynamic perfor-
mance is excellent for input frequencies up to the Nyquist
limit of 200kHz as shown in Figure 2b.
Figure 1. A
IN
Input
LTC1400 F01
SAMPLE
D
OUT
C
DAC
V
DAC
DAC
A
IN
C
SAMPLE
+
COMP
S
A
R
SAMPLE
S1
HOLD
Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT
Plot with 100kHz Input Frequency in Bipolar Mode
FREQUENCY (kHz)
0
40
80 100
140
180
20
60
120
160
200
A
LTC1400 F02a
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
f
SAMPLE
= 400kHz
f
SINAD = 72.5dB
THD = –82dB
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the effective resolution of an ADC and is directly related to
the S/(N + D) by the equation:
S N D
=
.
6 02
N
)
/
–1 76
相關(guān)PDF資料
PDF描述
LTC1400 Complete SO-8, 12-Bit,400ksps ADC with Shutdown(SO-8封裝,12位,400ksps,模數(shù)轉(zhuǎn)換器(帶關(guān)斷))
LTC1401C Complete SO-8, 12-Bit, 200ksps ADC with Shutdown
LTC1401CS8 Complete SO-8, 12-Bit, 200ksps ADC with Shutdown
LTC1401I Complete SO-8, 12-Bit, 200ksps ADC with Shutdown
LTC1401IS8 Complete SO-8, 12-Bit, 200ksps ADC with Shutdown
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LTC1400IS8PBF 制造商:Linear Technology 功能描述:ADC SAR 400ksps 12-Bit Serial SOIC8