參數(shù)資料
型號(hào)： LTC1402C
廠商： Linear Technology Corporation
英文描述： Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown
中文描述： 串行12位，2.2Msps采樣ADC，帶有關(guān)斷
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 251K
代理商： LTC1402C
14
LTC1402
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as
possible. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
as possible.
The LTC1402 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN+
and A
IN–
leads
will be rejected by the input CMRR. The A
IN–
input can be
used as a ground sense for the A
IN+
input; the LTC1402 will
hold and convert the difference voltage between A
IN+
and
A
IN–
. The leads to A
IN+
(Pin 3) and A
IN–
(Pin 4) should be
kept as short as possible. In applications where this is not
possible, the A
IN+
and A
IN–
traces should be run side-by-
side to cancel noise coupling.
SUPPLY BYPASSING
High quality, low series resistance 10
μ
F ceramic bypass
capacitors should be used at the V
DD
and V
REF
pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively, 10
μ
F tantalum capaci-
tors in parallel with 0.1
μ
F ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
POWER-DOWN MODES
Upon power-up, the LTC1402 is initialized to the active
state and is ready for conversion. The Nap and Sleep Mode
waveforms show the power-down modes for the LTC1402.
APPLICATIO
S I
N
FOR
ATIO
U
D
OUT
is binary with 1LSB = FS/4096 = 4.096V/4096 =
1.0mV. In applications where absolute accuracy is impor-
tant, offset and full-scale errors can be adjusted to zero.
Offset error must be adjusted before full-scale error. In
Figure 9b, zero offset is achieved by adjusting the offset
applied to the A
IN–
input. For zero offset error apply
–0.5mV (i.e., –0.5LSB) to A
IN+
and adjust the offset at the
A
IN–
input using R8 until the output code flickers between
0000 0000 0000 and 0000 0000 0001. For full-scale ad-
justment in Figures 9a and 9b, apply an input voltage of
2.0465V (FS – 1.5LSBs) to A
IN+
and adjust R5 until the
output code flickers between 1111 1111 1110 and 1111
1111 1111.
W
U
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1402, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all
other analog grounds should be connected directly to an
analog ground plane. Pin 9 (OGND) should be connected
near Pin13 (DGND), where the analog ground plane ties to
the logic system ground. The V
REF
bypass capacitor and
the DV
DD
bypass capacitor should also be connected to
this analog ground plane, see Figure 10. No other digital
grounds should be connected to this analog ground plane.
Figure 10. Power Supply Grounding Practice
1402 F10
A
IN+
AGND2
AGND1
V
REF
AV
DD
DV
DD
1
OV
DD
D
OUT
OGND
LTC1402
DIGITAL
SYSTEM
SYSTEM
GROUND
10
μ
F
10
μ
F
ANALOG
INPUT
CIRCUITRY
6
14
5
4
12
13
9
10
12
3V TO 5V
DGND
3
A
IN–
V
SS
2
ANALOG GROUND PLANE
10
μ
F
+
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