LTC1403-1/LTC1403A-1
9
14031fc
BLOCK DIAGRAM
PIN FUNCTIONS
AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates
fully differentially with respect to AIN– with a –1.25V to
1.25V differential swing with respect to AIN– and a 0V to
VDD common mode swing.
AIN– (Pin 2): Inverting Analog Input. AIN– operates fully
differentially with respect to AIN+ with a 1.25V to –1.25V
differential swing with respect to AIN+ and a 0V to VDD
common mode swing.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND
and to a solid analog ground plane with a 10F ceramic
capacitor (or 10F tantalum in parallel with 0.1F ceramic).
Can be overdriven by an external reference between 2.55V
and VDD.
GND (Pins 4, 5, 6, Exposed Pad Pin 11): Ground. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND and to a
solid analog ground plane with a 10F ceramic capacitor
(or 10F tantalum in parallel with 0.1F ceramic). Keep in
mindthatinternalanalogcurrentsanddigitaloutputsignal
currents flow through this pin. Care should be taken to
place the 0.1F bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each of
output data words represents the difference between
AIN+ and AIN– analog inputs at the start of the previous
conversion. The output format is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (≤3V) and 3V CMOS levels. One
or more pulses wake from sleep.
CONV(Pin10):ConvertStart.Holdstheanaloginputsignal
and starts the conversion on the rising edge. Responds
to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK
in fixed high or fixed low state start Nap mode. Four or
more pulses with SCK in fixed high or fixed low state start
Sleep mode.
14031 BD
–
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC1403A-1
VREF
10F
AIN–
AIN+
14-BIT ADC
3V
10F
14
14-BIT
LA
TCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
5
6
11