TYPICAL PERFORMANCE CHARACTERIS" />
參數(shù)資料
型號(hào): LTC1406CGN#TR
廠商: Linear Technology
文件頁(yè)數(shù): 12/16頁(yè)
文件大?。?/td> 0K
描述: IC ADC 8BIT 20MSPS SAMPLE 24SSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 225mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
5
LTC1406
TYPICAL PERFORMANCE CHARACTERISTICS
UW
OUTPUT CODE
0
INL
EOC
ERROR
(LSB)
256
1406 G07
64
128
192
1.0
0.5
0
–0.5
–1.0
32
96
160
224
Supply Current vs
Sampling Frequency
SAMPLING FREQUENCY (Hz)
100k
SUPPLY
CURRENT
(mA)
35
30
25
20
15
10
5
0
1M
10M
1406 G09
20M
INPUT FREQUENCY (Hz)
100k
SPURIOUS-FREE
DYNAMIC
RANGE
(dB)
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G04
Intermodulation Distortion Plot
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AMPLITUDE
(dB)
1406 G05
0123
4
5
67
8
9
10
fSAMPLE = 20MHz
fIN1 = 3.500977MHz
fIN2 = 3.598633MHz
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
DNL
EOC
ERROR
(LSB)
256
1406 G06
64
128
192
1.0
0.5
0
–0.5
–1.0
32
96
160
224
INPUT FREQUENCY (Hz)
100k
COMMON
MODE
REJECTION
(dB)
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G08
Input Common Mode Rejection
vs Input Frequency
Integral Nonlinearity
vs Output Code
Spurious-Free Dynamic Range
vs Input Frequency
PIN FUNCTIONS
UU
U
OGND (Pin 1): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OVDD (Pin 2): Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10
F tantalum in parallel with 0.1F or 10F
ceramic.
SHDN (Pin 3): Power Shutdown Input. Logic low selects
shutdown.
VBIAS (Pin 4): Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10
F tantalum in par-
allel with 0.1
F or 10F ceramic.
VREF (Pin 5): External 2.5V Reference Input. Bypass to
analog ground plane with 10
F tantalum in parallel with
0.1
F or 10F ceramic.
AGND (Pin 6): Analog Ground. Tie to analog ground plane.
AIN+ (Pin 7): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN
+) – (AIN–)] = –1V.
AIN– (Pin 8): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN
+) – (AIN–)] = –1V. For single-
ended operation, tie AIN– to a DC voltage (e.g., VREF).
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