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參數(shù)資料
| 型號(hào)： | LTC1406IGN#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 8BIT SAMPLING 24SSOP |
| 標(biāo)準(zhǔn)包裝： | 55 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 225mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 1349 (CN2011-ZH PDF) |
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13
LTC1406
APPLICATIONS INFORMATION
WU
U
microprocessor bus, it is possible to get errors in the con-
version results. These errors are due to feedthrough from
the microprocessor to the comparators. The problem can
be eliminated by forcing the microprocessor into a wait
state during conversion or by using three-state buffers to
isolate the ADC data bus.
The LTC1406 has differential inputs to minimize noise cou-
pling. Common mode noise on the AIN+ and AIN– leads will
be rejected by the input CMRR. The LTC1406 will hold and
convert the difference voltage between AIN
+ and AIN–. The
leads to AIN+ (Pin 7) and AIN– (Pin 8) should be kept as
short as possible. In applications where this is not pos-
sible, the AIN
+ and AIN– traces should be run side by side
to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10
F bypass
capacitors should be used at the VDD, VCM and VREF pins
as shown in the Typical Application on the first page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively, 10
F tantalum
capacitors in parallel with 0.1
F ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 12a, 12b, 12c and 12d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
shutdown. It may also be desirable to isolate the data out-
put pins from the bus to reduce the load capacitance. To
resume normal operation the SHDN pin must be brought
high and typically 20 clock cycles must be performed at a
sample rate above 10kHz before the output data will be
valid.
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best per-
formance from the LTC1406, a printed circuit board with
ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 1 (OGND), Pin 6 (AGND), Pin 10 (AGND) and Pin 11
(DGND) and all other analog grounds should be connected
to this single analog ground point. The VCM, VREF, DVDD
and OVDD bypass capacitors should also be connected to
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. In some appli-
cations it may be desirable to connect the OVDD to the logic
system supply and OGND to the logic system ground. In
these cases OVDD should be bypassed to OGND instead of
the analog ground plane.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as pos-
sible. In applications where the ADC data outputs and
control signals are connected to a continuously active
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