參數(shù)資料
型號(hào): LTC1406IGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Low Power, 8-Bit, 20Msps, Sampling A/D Converter
中文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24
封裝: 0.150 INCH, PLASTIC, SSOP-24
文件頁(yè)數(shù): 5/16頁(yè)
文件大小: 447K
代理商: LTC1406IGN
5
LTC1406
TYPICAL PERFOR
M
A
CE CHARACTERISTICS
U
OUTPUT CODE
0
I
256
1406 G07
64
128
192
1.0
0.5
0
–0.5
–1.0
32
96
160
224
Supply Current vs
Sampling Frequency
SAMPLING FREQUENCY (Hz)
100k
S
35
30
25
20
15
10
5
0
1M
10M
1406 G09
20M
INPUT FREQUENCY (Hz)
100k
S
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G04
Intermodulation Distortion Plot
0
FREQUENCY (MHz)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
A
1406 G05
0
1
2
3
4
5
6
7
8
9
10
f
SAMPLE
= 20MHz
f
IN1
f
IN2
= 3.598633MHz
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
D
256
1406 G06
64
128
192
1.0
0.5
0
–0.5
–1.0
32
96
160
224
INPUT FREQUENCY (Hz)
100k
C
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G08
Input Common Mode Rejection
vs Input Frequency
Integral Nonlinearity
vs Output Code
Spurious-Free Dynamic Range
vs Input Frequency
PI
FU
CTIO
N
S
U
U
OGND (Pin 1):
Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OV
DD
(Pin 2):
Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10
μ
F tantalum in parallel with 0.1
μ
F or 10
μ
F
ceramic.
SHDN (Pin 3):
Power Shutdown Input. Logic low selects
shutdown.
V
BIAS
(Pin 4):
Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10
μ
F tantalum in par-
allel with 0.1
μ
F or 10
μ
F ceramic.
V
REF
(Pin 5):
External 2.5V Reference Input.
Bypass to
analog ground plane with 10
μ
F tantalum in parallel with
0.1
μ
F or 10
μ
F ceramic.
AGND (Pin 6):
Analog Ground. Tie to analog ground plane.
A
IN+
(Pin 7):
±
1V Input. The maximum output code
occurs when [(A
IN+
) – (A
IN–
)] = 1V. The minimum output
code occurs when [(A
IN+
) – (A
IN–
)] = –1V.
A
IN–
(Pin 8):
±
1V Input. The maximum output code
occurs when [(A
IN+
) – (A
IN–
)] = 1V. The minimum output
code occurs when [(A
IN+
) – (A
IN–
)] = –1V. For single-
ended operation, tie A
IN–
to a DC voltage (e.g., V
REF
).
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PDF描述
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