參數(shù)資料
型號(hào): LTC1407IMSE
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): ADC
英文描述: Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling Simultaneous Sampling
中文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝: PLASTIC, MSOP-10
文件頁(yè)數(shù): 1/24頁(yè)
文件大小: 443K
代理商: LTC1407IMSE
1
LTC1407/LTC1407A
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
1407f
I
3Msps Sampling ADC with Two Simultaneous
Differential Inputs
I
1.5Msps Throughput per Channel
I
Low Power Dissipation: 14mW (Typ)
I
3V Single Supply Operation
I
2.5V Internal Bandgap Reference with External
Overdrive
I
3-Wire Serial Interface
I
Sleep (10
μ
W) Shutdown Mode
I
Nap (3mW) Shutdown Mode
I
80dB Common Mode Rejection at 100kHz
I
0V to 2.5V Unipolar Input Range
I
Tiny 10-Lead MS Package
APPLICATIU
, LTC and LT are registered trademarks of Linear Technology Corporation.
I
Telecommunications
I
Data Acquisition Systems
I
Uninterrupted Power Supplies
I
Multiphase Motor Control
I
I & Q Demodulation
I
Industrial Control
The LTC
1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs
with two 1.5Msps simultaneously sampled differential
inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10
μ
W.
The combination of speed, low power and tiny package
makes the LTC1407/LTC1407A suitable for high speed,
portable applications.
The LTC1407/LTC1407A contain two separate differential
inputs that are sampled simultaneously on the rising edge
of the CONV signal. These two sampled inputs are then
converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differen-
tially. The absolute voltage swing for CH0
+
, CH0
, CH1
+
and CH1
extends from ground to the supply voltage.
The serial interface sends out the two conversion results in
32 clocks for compatibility with standard serial interfaces.
+
1
2
7
3
6
S & H
+
4
5
S & H
GND
11
EXPOSED PAD
V
REF
10
μ
F
CH0
CH0
+
CH1
CH1
+
3V
10
μ
F
LTC1407A
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
V
DD
SDO
CONV
SCK
1407A BD
3Msps
14-BIT ADC
1
1
FREQUENCY (MHz)
0.1
–80
T
–74
–68
–62
–56
1
10
100
1407 G02
–86
–92
–98
–104
–50
–44
THD
3rd
2nd
FEATURES
DESCRIPTIOU
BLOCK DIAGRA
THD, 2nd and 3rd
vs Input Frequency
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