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參數(shù)資料
| 型號(hào)： | LTC1410IG#TR |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS SMP 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
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13
LTC1410
APPLICATIONS INFORMATION
WU
U
Power Shutdown
The LTC1410 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias
currents are shut down and only leakage current re-
mains –– about 1
A. Wake-up time from Sleep mode is
t3
NAP/SLP
SHDN
1410 F12a
Figure 12a. NAP/SLP to SHDN Timing
Figure 12b. SHDN to CONVST Wake-Up Timing
much slower since the reference circuit must power up
and settle to 0.01% for full 12-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
10ms with the recommended 10
F capacitor.
Shutdown is controlled by Pin 21 (SHDN), the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 20 (NAP/SLP); high selects Nap.
t2
t1
CS
CONVST
RD
1410 F12
t4
SHDN
CONVST
1410 F12b
Figure 13. CS to CONVST Setup Timing
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Figures 14 through 18 show several different modes of
operation. In modes 1a and 1b (Figures 14 and 15) CS
and RD are both tied low. The falling edge of CONVST
starts the conversion. The data outputs are always enabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
In mode 2 (Figure 16) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
In slow memory and ROM modes (Figures 17 and 18) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
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