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參數(shù)資料
| 型號(hào)： | LTC1410ISW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT SAMPLNG 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
11
LTC1410
APPLICATIONS INFORMATION
WU
U
1
2
3
4
5
0.1
F
10
F
ANALOG
INPUT
1410 F08b
LT1019A-2.5
VOUT
VIN
5V
+AIN
–AIN
VREF
REFCOMP
AGND
LTC1410
Figure 8b. Using the LT1019-2.5 as an External Reference
easily overdriven in applications where an external refer-
ence is required. The reference amplifier provides buffer-
ing between the internal reference and the capacitive DAC.
The reference amplifier compensation pin REFCOMP
(Pin 4), must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 1
F or
greater. For the best noise performance, a 10
F tantalum
in parallel with 0.1
F ceramic is recommended.
The VREF pin can be driven with an external reference
(Figure 8b), a DAC or other means to provide input span
adjustment. The VREF should be kept in the range of 2.25V
to 2.75V for specified linearity.
Full-Scale and Offset Adjustment
Figure 9 shows the ideal input/output characteristics for
the LTC1410. The code transitions occur midway between
successive integer LSB values (i.e., – FS + 0.5LSB,
– FS + 1.5LSB, – FS + 2.5LSB, . . . FS – 1.5LSB,
FS – 0.5LSB).The output is two’s complement binary
with 1LSB = [(+FS) – (– FS)]/4096 = 5V/4096 = 1.22mV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 10
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the – AIN input. For zero offset error apply
– 0.61mV (i.e., – 0.5LSB) at +AIN and adjust the offset at
the – AIN input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS – 1.5LSBs) is
applied to AIN and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1410, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. Particular care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
ANALOG
INPUT
1410 F10
1
2
3
R4
100
R2
50k
R3
47k
–5V
R6
24k
R1
50k
R5
47k
4
5
0.1
F
10
F
+AIN
–AIN
VREF
REFCOMP
AGND
LTC1410
Figure 10. Offset and Full-Scale Adjust Circuit
INPUT VOLTAGE, (+AIN) – (–AIN) (V)
0V
OUTPUT
CODE
–1
LSB
1410 F09
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS – LSB
–FS
FS = 2.5V
1LSB =
2FS
4096
Figure 9. LTC1410 Transfer Characteristics
相關(guān)PDF資料 |
PDF描述 |
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| LTC1410ISW | IC A/D CONV 12BIT SAMPLNG 28SOIC |
| VE-2N2-IW-S | CONVERTER MOD DC/DC 15V 100W |
| VE-2N2-CU-F4 | CONVERTER MOD DC/DC 15V 200W |
| VE-2N2-CU-F3 | CONVERTER MOD DC/DC 15V 200W |
| VE-2N2-CU-F2 | CONVERTER MOD DC/DC 15V 200W |
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