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參數(shù)資料
| 型號： | LTC1411IG#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT 2.5MSPS 36SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 其它名稱： | LTC1411IGTR |
12
LTC1411
1411f
Figure 7 shows a typical reference, the LT1019A-2.5
connected to the LTC1411. This will provide an improved
drift (equal to the maximum 5ppm/
°C of the LT1019A-2.5).
By driving the SLP pin low for Sleep mode, the ADC shuts
down to less than 1
A. After release from the Sleep mode,
the ADC needs 210ms (10
F bypass capacitor on the
REFCOM2 pin) to wake up.
In Nap mode, all the power is off except the internal refer-
ence which is still active for the other external circuitry. In
this mode the ADC draws about 2mA instead of 39mA (for
minimum power, the logic inputs must be within 600mV
from the supply rails). The wake-up time from Nap mode
to active state is 250ns as shown in Figure 9.
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1411, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure that the digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track.
APPLICATIO S I FOR ATIO
WU
UU
Figure 9. NAP to CONVST Wake-Up Timing
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1411 with the LT1019A-2.5
Figure 8. Overrange and Underrange Logic
Table 2. Out-of-the-Range Truth Table
OTR
D13 (MSB)
ANALOG INPUT
0
In Range
0
1
In Range
1
0
Overrange
1
Underrange
3
2
6
4
1
2
4
7, 8, 9
INPUT RANGE:
0.7V TO 4.3V
10
F
1411 F07
LT1019A-2.5
VIN
GND
VOUT
5V
LTC1411
AIN+
AIN
–
AGND
REFIN
Digital Interface
The ADC has a very simple digital interface with only one
control input, CONVST. A logic low applied to the CONVST
input will initiate a conversion. The ADC presents digital
data in 2’s complement format with bipolar zero set by the
voltage applied to the AIN– pin.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 260ns. With the typical acquisition
time of 100ns, a throughput sampling rate of 2.5Msps is
guaranteed.
Out-of-the-Range Signal (OTR)
The LTC1411 has a digital output, OTR, that indicates if an
analog input signal is out of range. The OTR remains
low when the analog input is within the specified range.
Once the analog signal goes to the most negative input
(1000 0000 0000 00) or 64LSB above the specified most
positive input, OTR will go high. By NORing D13 (MSB)
and its complement with OTR, overrange and underrange
can be detected as shown in Figure 8. Table 2 is the truth
table of the out-of-the-range circuit in Figure 8.
Power Shutdown (Sleep and Nap Modes)
The LTC1411 provides two shutdown features that will
save power when the ADC is inactive.
OTR
D13
“1” FOR OVERRANGE
U1-A
U1-B
U1-A, U1-B = 74HC OR EQUIVALENT
“1” FOR UNDERRANGE
1411 F08
t1
NAP
CONVST
1411 F09
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