APPLICATIONS INFOR
參數(shù)資料
型號(hào)： LTC1418IN#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 0K
描述： IC A/D CONV 14BIT SRL&PAR 28-DIP
標(biāo)準(zhǔn)包裝： 14
位數(shù)： 14
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.5mW 單極；31.5mW 雙極
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 通孔
封裝/外殼： 28-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 28-PDIP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
配用： DC178A-ND - BOARD SAR ADC LTC1418
18
LTC1418
APPLICATIONS INFORMATION
WU
U
Figure 14. CS to CONVST Set-Up Timing
t2
t1
CS
CONVST
RD
1418 F14
mode is much slower since the reference circuit must
power up and settle to 0.005% for full 14-bit accuracy.
Sleep mode wake-up time is dependent on the value of
the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 30ms with the recommended 10
F
capacitor. Shutdown is controlled by Pin 22 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin 25 (CS); low selects nap (see Figure
13b), high selects sleep.
t4
SHDN
CONVST
1418 F13a
Figure 13a. SHDN to CONVST Wake-Up Timing
t3
CS
SHDN
1418 F13b
Figure 13b. CS to SHDN Timing
Conversion Control
Conversion start is controlled by the CS and CONVST
inputs. A falling edge of CONVST pin will start a conversion
after the ADC has been selected (i.e., CS is low, see Figure
14). Once initiated, it cannot be restarted until the conver-
sion is complete. Converter status is indicated by the
BUSY output. BUSY is low during a conversion.
Data Output
The data format is controlled by the SER/PAR input pin;
logic low selects parallel output format. In parallel mode
the 14-bit data output word D0 to D13 is updated at the end
of each conversion on Pins 6 to 13 and Pins 15 to 20. A
logic high applied to SER/PAR selects the serial formatted
data output and Pins 16 to 20 assume their serial function,
Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel
or serial data formats, outputs will be active only when CS
and RD are low. Any other combination of CS and RD will
three-state the output. In unipolar mode (VSS = 0V) the
data will be in straight binary format (corresponding to the
unipolar input range). In bipolar mode (VSS = –5V), the
data will be in two’s complement format (corresponding to
the bipolar input range).
Parallel Output Mode
Parallel mode is selected with a logic 0 applied to the
SER/PAR pin. Figures 15 through 19 show different modes
of parallel output operation. In modes 1a and 1b (Figures
15 and 16) CS and RD are both tied low. The falling edge
of CONVST starts the conversion. The data outputs are
always enabled and data can be latched with the BUSY
rising edge. Mode 1a shows operation with a narrow logic
low CONVST pulse. Mode 1b shows a narrow logic high
CONVST pulse.
In mode 2 (Figure 17) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared databus.
In slow memory and ROM modes (Figures 18 and 19), CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor takes RD (= CONVST)
low and starts the conversion. BUSY goes low forcing the
processor into a wait state. The previous conversion result
appears on the data outputs. When the conversion is
complete, the new conversion results appear on the data
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