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參數(shù)資料
| 型號： | LTC1419ACG#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 800KSPS SHDN 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 800k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 240mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
7
LTC1419
1419fb
Load Circuits for Access Timing
Load Circuits for Output Float Delay
TEST CIRCUITS
1k
CL
DBN
(A) Hi-Z TO VOH
(B) Hi-Z TO VO
DBN
1k
5V
1419 TC01
1k
DBN
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
DBN
1k
5V
1419 TC02
APPLICATIONS INFORMATION
WU
U
CONVERSION DETAILS
The LTC1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the + AIN and –AIN inputs are con-
nected to the sample-and-hold capacitors (CSAMPLE) dur-
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 200ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the CSAMPLE capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the + AIN and – AIN input charges.
The SAR contents (a 14-bit data word) which represents
the difference of + AIN and – AIN are loaded into the 14-bit
output latches.
DYNAMIC PERFORMANCE
The LTC1419 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
Figure 1. Simplified Block Diagram
COMP
+CSAMPLE
–CDAC
D13
D0
ZEROING SWITCHES
HOLD
+AIN
–AIN
+CDAC
–CSAMPLE
14
1419 F01
+
–
SAR
OUTPUT
LATCHES
+VDAC
–VDAC
HOLD
SAMPLE
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