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參數(shù)資料
| 型號： | LTC1419ACG |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標準包裝： | 47 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 800k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 240mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
4
LTC1419
1419fb
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +AIN input with – AIN grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 650ns after the start of the conversion or after BUSY rises.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PDIS
Power Dissipation
●
150
240
mW
Nap Mode
SHDN = 0V, CS = 0V
7.5
12
mW
Sleep Mode
SHDN = 0V, CS = 5V
1.2
mW
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
800
kHz
tCONV
Conversion Time
●
950
1150
ns
tACQ
Acquisition Time
●
90
300
ns
tACQ + CONV
Acquisition + Conversion Time
●
1040
1250
ns
t1
CS to RD Setup Time
(Notes 9, 10)
●
0ns
t2
CS
↓ to CONVST↓ Setup Time
(Notes 9, 10)
●
40
ns
t3
CS
↓ to SHDN↓ Setup Time
(Notes 9, 10)
40
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time (Note 10)
400
ns
t5
CONVST Low Time
(Notes 10, 11)
●
40
ns
t6
CONVST to BUSY Delay
CL = 25pF
20
ns
●
50
ns
t7
Data Ready Before BUSY
↑
20
50
ns
●
15
ns
t8
Delay Between Conversions
(Note 10)
●
40
ns
t9
Wait Time RD
↓ After BUSY↑
(Note 9)
●
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
15
25
ns
●
35
ns
CL = 100pF
20
35
ns
●
50
ns
t11
Bus Relinquish Time
10
20
ns
0
°C ≤ TA ≤ 70°C
●
25
ns
–40
°C ≤ TA ≤ 85°C
●
30
ns
t12
RD Low Time
●
t10
ns
t13
CONVST High Time
●
40
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless
otherwise specified.
The
● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
W
U
The
● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
U
W
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