參數(shù)資料
型號: LTC1419CG
廠商: Linear Technology
文件頁數(shù): 17/20頁
文件大?。?/td> 0K
描述: IC A/D CONV 14BIT SAMPLNG 28SSOP
標(biāo)準(zhǔn)包裝: 47
位數(shù): 14
采樣率(每秒): 800k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 240mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
產(chǎn)品目錄頁面: 1346 (CN2011-ZH PDF)
6
LTC1419
1419fb
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND
with 10
F tantalum in parallel with 0.1F or 10F
ceramic.
DVDD (Pin 27): 5V Positive Supply. Short to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
with 10
F tantalum in parallel with 0.1F or 10F
ceramic.
+AIN (Pin 1): ±2.5V Positive Analog Input.
–AIN (Pin 2): ±2.5V Negative Analog Input.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND
with 1
F.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 10
F tantalum in parallel with 0.1F or 10F
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The
output format is 2’s complement.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The
output format is 2’s complement.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
14-BIT CAPACITIVE DAC
COMP
REF AMP
2.5V REF
REFCOMP
(4.096V)
CSAMPLE
D13
D0
BUSY
CONTROL LOGIC
CS
CONVST
RD
SHDN
INTERNAL
CLOCK
ZEROING SWITCHES
DVDD
VSS
AVDD
+AIN
–AIN
VREF
AGND
DGND
14
1419 BD
+
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
2k
FU CTIO AL BLOCK DIAGRA
UU
W
UU
U
PI FU CTIO S
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