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參數(shù)資料
| 型號(hào)： | LTC1421-2.5CG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 14-bit, 5V, 200KSPS, 4-Channel Unipolar ADC 20-SOIC 0 to 70 |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 464K |
| 代理商： | LTC1421-2.5CG |
5
LTC1421/LTC1421-2.5
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
CPON Voltage vs Source Current
(Charge Pump On)
SOURCE CURRENT (mA)
0
0
C
1
2
3
4
5
–0.5
–1.0
–1.5
–2.0
1421 G10
–2.5
–3.0
V
CCLO
= 5V
V
CCHI
= 12V
I
CCLO
Supply Current
vs V
CCLO
Voltage
V
CCLO
VOLTAGE (V)
0
4
5
7
6
10
1421 G11
3
2
2
4
8
12
14
1
0
6
I
C
V
CCHI
= 12V
PI
FU
CTIO
N
S
U
U
CON1 (Pin 1):
TTL Level Input with a Pull-Up to V
CCLO
.
Together with CON2, it is used to indicate board connec-
tion. The pin must be tied to ground on the host side of the
connector. When using staggered connector pins, CON1
and CON2 must be the shortest and must be placed at
opposite corners of the connector. Board insertion is
assumed after CON1 and CON2 are both held low for 20ms
after power-up.
CON2 (Pin 2):
TTL Level Input with a Pull-Up to V
CCLO
.
Together with CON1 it is used to indicate board connec-
tion.
POR (Pin 3):
TTL Level Input with a Pull-Up to V
CCLO
.
When the pin is pulled low for at least 20ms, a hard reset
is generated. Both V
OUTLO
and V
OUTHI
will turn off at a
controlled rate. A power-up sequence will not start until
the POR pin is pulled high. If POR is pulled high before
V
OUTLO
and V
OUTHI
are fully discharged, a power-up
sequence will not begin until the voltage at V
OUTLO
and
V
OUTHI
are below V
TRIP
. The electronic circuit breaker will
be reset by pulling POR low.
FAULT (Pin 4):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low when an overcur-
rent fault is detected at V
OUTLO
or V
OUTHI
.
DISABLE (Pin 5):
CMOS Output. The signal is used to
disable the board’s data bus during insertion or removal.
PWRGD (Pin 6):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low immediately after
V
OUTLO
falls below its reset threshold voltage. The pin is
pulled high immediately after V
OUTLO
rises above its reset
threshold voltage.
RESET (Pin 7):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low when a reset
condition is detected. A reset will be generated when any
of the following conditions are met: Either CON1 or CON2
is high, POR is pulled low, V
CCLO
or V
CCHI
are below their
respective undervoltage lockout thresholds, PWRGD goes
low or an overcurrent fault is detected at V
OUTLO
or
V
OUTHI
. RESET will go high 200ms after PWRGD goes
high. On power failure, RESET will go low 32
μ
s after
PWRGD goes low.
REF (Pin 8):
The Reference Voltage Output. V
OUT
= 1.232V
±
1%. The reference can source up to 5mA of current. A
1
μ
F bypass capacitor is recommended.
CPON (Pin 9):
CMOS Output That Can Be Pulled Below
Ground. CPON is pulled high when the internal charge
pumps for GATELO and GATEHI are turned on. CPON is
pulled low when the charge pumps are turned off. The pin
can be used to control an external MOSFET for a –5V to
–12V supply.
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