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參數(shù)資料
| 型號(hào)： | LTC1429CS8-4 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | Clock-Synchronized Switched Capacitor Regulated Voltage Inverter |
| 中文描述： | SWITCHED CAPACITOR REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | LTC1429CS8-4 |
8
LTC1429
APPLICATIO
S I
FOR
ATIO
U
the clock pulse finishes. When this happens, the compara-
tor will allow a few complete pulses through, then over-
correct and disable the charge pump until the output
drops below the set point. Under these conditions, the
output will remain in regulation, but the output ripple will
increase as the comparator “hunts” for the correct value.
To help prevent this from happening, an external capacitor
can be connected from ADJ (or COMP for fixed output
parts) to ground to compensate for external parasitics and
increase the regulation loop bandwidth (Figure 5). This
sounds counter-intuitive until we remember that the inter-
nal reference is generated with respect to OUT, not ground.
The feedback loop actually sees ground as its “output”;
thus the compensation capacitor should be connected
across the “top” of the resistor divider from ADJ (or
COMP) to ground. By the same token, avoid adding
capacitance between ADJ (or COMP) and V
OUT
; this will
slow down the feedback loop and increase output ripple.
A 1000pF capacitor from ADJ or COMP to ground will
compensate the loop properly under most conditions.
W
U
U
current. The clock signal should have a duty cycle between
40% and 60% for proper regulation loop performance.
The LTC 1429 can be shut down by stopping the clock. An
internal circuit monitors the time between clock edges at
the SYNC/SD pin. If a 10
μ
s period elapses without a rising
or falling edge, LTC1429 assumes the clock has stopped
and goes into shutdown mode and the quiescent current
drops to below 1
μ
A. The next clock edge at the SYNC/SD
pin will reawaken the LTC1429. At clock frequencies
below 50kHz (50% duty cycle) the LTC1429 may enter
shutdown mode briefly during each clock cycle causing
erratic operation. Minimum operating frequency should
be kept above 60kHz (above 100kHz with V
CC
> 5) to
prevent this from happening.
Radiation from the clock signal at the SYNC/SD pin can
interfere with the feedback node at the ADJ/COMP pin
causing errors in the output voltage. The clock line should
be routed away from the circuitry at the ADJ/COMP pin
and should be shielded with a ground plane or with coaxial
cable. A compensation capacitor from the ADJ/COMP pin
to ground can also help to reduce this effect: 0.001
μ
F is
adequate for most applications.
OUTPUT FILTERING
If extremely low output ripple (<10mV) is required, addi-
tional output filtering is required. Because the LTC1429
uses a high, external control switching frequency, fairly
low value RC or LC networks can be used at the output to
effectively filter the output ripple. With F
SYNC
= 700kHz, a
10
series output resistor and a 3.3
μ
F capacitor will cut
output ripple to below 3mV (see Figure 6). Further reduc-
COMP 1
1.24V
R2
V
OUT
ADJ/COMP
RESISTORS ARE INTERNAL
FOR FIXED OUTPUT PARTS
LTC1429 F05
R1
C
C
1000pF
TO CHARGE
PUMP
REF
+
–
Figure 5. Regulator Loop Compensation
EXTERNAL CLOCK
The LTC1429 requires an external clock to operate. This
clock signal should be TTL or CMOS compatible and
should be applied to the SYNC/SD pin. The external clock
allows the user to control the frequency at which the
LTC1429 operates, preventing it from interfering with
other frequency-sensitive circuitry. The LTC1429 can be
synchronized to any frequency between 60kHz (100kHz
for V
CC
> 5) and 2MHz. Higher clock frequencies can help
reduce output ripple at the cost of additional quiescent
LTC1429CS8-4
V
CC
SYNC/SD
5V
C1
+
C1
–
4
1
6
8
5
2
3
OUT
0.1
μ
F
1000pF
3.3
μ
F
10
COMP
LTC1429 F06
GND
+
3.3
μ
F
V
OUT
= –4V
+
0.1
μ
F
F
SYNC
= 700kHz
Figure 6. Output Filter Cuts Ripple Below 3mV
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