![](http://datasheet.mmic.net.cn/330000/LTC1430CN8_datasheet_16428949/LTC1430CN8_4.png)
4
LTC1430
G1 (Pin 1/Pin 1):
Driver Output 1. Connect this pin to the
gate of the upper N-channel MOSFET, M1. This output will
swing from PV
CC1
to PGND. It will always be low when G2
is high.
PV
CC1
(Pin 2/Pin 2):
Power V
CC
for Driver 1. This is the
power supply input for G1. G1 will swing from PGND to
PV
CC1
. PV
CC1
must be connected to a potential of at least
PV
CC
+ V
GS(ON)
(M1). This potential can be generated
using an external supply or a simple charge pump con-
nected to the switching node between the upper MOSFET
and the lower MOSFET; see Applications Information for
details.
PGND (Pin 3/Pin 3):
Power Ground. Both drivers return to
this pin. It should be connected to a low impedance ground
in close proximity to the source of M2. 8-lead parts have
PGND and GND tied together at pin 3.
GND (Pin 4/Pin 3):
Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, GND should be connected to
PGND right at the LTC1430. 8-lead parts have PGND and
GND tied together internally at pin 3.
SENSE
–
, FB, SENSE
+
(Pins 5, 6, 7/Pin 4):
These three
pins connect to the internal resistor divider and to the
internal feedback node. To use the internal divider to set
the output voltage to 3.3V, connect SENSE
+
to the positive
terminal of the output capacitor and SENSE
–
to the nega-
tive terminal. FB should be left floating in applications that
use the internal divider. To use an external resistor divider
to set the output voltage, float SENSE
+
and SENSE
–
and
connect the external resistor divider to FB.
SHDN (Pin 8/Pin 5):
Shutdown. A TTL compatible low
level at SHDN for longer than 50
μ
s puts the LTC1430 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10
μ
A max. A TTL compatible high level at SHDN
allows the part to operate normally.
SS (Pin 9/NA):
Soft-Start. The SS pin allows an external
capacitor to be connected to implement a soft-start func-
tion. An external capacitor from SS to ground controls the
start-up time and also compensates the current limit loop,
allowing the LTC1430 to enter and exit current limit
cleanly. See Applications Information for more details.
COMP (Pin 10/Pin 6):
External Compensation. The COMP
pin is connected directly to the output of the error amplifier
and the input of the PWM. An RC network is used at this
node to compensate the feedback loop to provide opti-
mum transient response. See Applications Information for
compensation details.
FREQSET (Pin 11/NA):
Frequency Set. This pin is used to
set the free running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 200kHz.
A resistor from FREQSET to ground will speed up the
oscillator; a resistor to V
CC
will slow it down. See Applica-
tions Information for resistor selection details.
I
MAX
(Pin 12/NA):
Current Limit Set. I
MAX
sets the thresh-
old for the internal current limit comparator. If I
FB
drops
below I
MAX
with G1 on, the LTC1430 will go into current
limit. I
MAX
has a 12
μ
A pull-down to GND. It can be adjusted
with an external resistor to PV
CC
or an external voltage
source.
I
FB
(Pin 13/NA):
Current Limit Sense. Connect to the
switched node at the source of M1 and the drain of M2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I
FB
. This pin can be
taken up to 18V above GND without damage.
V
CC
(Pin 14/Pin 7):
Power Supply. All low power internal
circuits draw their supply from this pin. Connect to a clean
power supply, separate from the main PV
CC
supply at the
drain of M1. This pin requires a 4.7
μ
F bypass capacitor.
8-lead parts have V
CC
and PV
CC2
tied together at pin 7 and
require a 10
μ
F bypass to GND.
PV
CC2
(Pin 15/Pin 7):
Power V
CC
for Driver 2. This is the
power supply input for G2. G2 will swing from GND to
PV
CC2
. PV
CC2
is usually connected to the main high power
supply. The 8-lead parts have V
CC
and PV
CC2
tied together
at pin 7 and require a 10
μ
F bypass to GND.
G2 (Pin 16/Pin 8):
Driver Output 2. Connect this pin to the
gate of the lower N-channel MOSFET, M2. This output will
swing from PV
CC2
to PGND. It will always be low when G1
is high.
(16-Lead Package/8-Lead Package)
PIU