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參數(shù)資料
| 型號： | LTC1439IGW |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators |
| 中文描述： | 2 A DUAL SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO36 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 596K |
| 代理商： | LTC1439IGW |
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18
LTC1438/LTC1439
APPLICATIO
S I
FOR
ATIO
U
Functional Diagram. In a hard short (V
OUT
= 0V) the current
will be reduced to approximately 25% of the maximum
output current. This technique may be used for all applica-
tions with regulated output voltages of 1.8V or greater.
W
U
U
Phase-Locked Loop and Frequency Synchronization
The LTC1439 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage-controlled oscillator is
±
30% around the center
frequency f
O
.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range,
f
H
, is equal to the capture range,
f
C:
f
H
=
f
C
=
±
0.3 f
O
.
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLL LPF pin. A simplified block
diagram is shown in Figure 8.
If the external frequency f
PLLIN
is greater than the oscilla-
tor frequency f
0SC
, current is sourced continuously, pull-
ing up the PLL LPF pin. When the external frequency is less
than f
0SC
, current is sunk continuously, pulling down the
PLL LPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLL LPF pin is adjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
Figure 7. Operating Frequency vs V
PLLLPF
V
PLLLPF
(V)
0
N
1.3f
O
0.7f
O
1438 F07
1.5
2.0
1.0
0.5
2.5
f
O
The value of C
OSC
is calculated from the desired operating
frequency (f
O
). Assuming the phase-locked loop is locked
(V
PLLLPF
= 1.19V):
Frequency (kHz)
C
pF
OSC
(
)
=
2.1(10 )
11
Stating the frequency as a function of V
PLLLPF
and C
OSC
:
(
8 4 10
. (
Frequency kHz
C
pF
( )
+
A
AV
V
OSC
PLLLPF
2 4
.
)
=
[
]
+
+
11
1
17
18
2000
8
)
μ
μ
PLLIN*
SGND
50k
1438 F08
PLL LPF*
*LTC1439 ONLY
C
OSC
PHASE
DETECTOR
OSC
R
LP
C
LP
C
OSC
EXTERNAL
FREQUENCY
2.4V
DIGITAL
PHASE/
FREQUENCY
DETECTOR
Figure 8. Phase-Locked Loop Block Diagram
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