參數(shù)資料
型號(hào): LTC1456
廠商: Linear Technology Corporation
英文描述: Low-Power LinCMOS(TM) Quad Comparator with Totem Pole Output 14-SOIC -55 to 125
中文描述: 12位軌至軌微DAC,具有清除輸入
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 148K
代理商: LTC1456
5
LTC1456
CLK (Pin 1):
The Serial Interface Clock. Internal Schmitt
trigger on this input allows direct optocoupler interface.
D
IN
(Pin 2):
The Serial Interface Data. Data on the D
IN
pin
is latched into the shift register on the rising edge of the
serial clock.
CS/LD (Pin 3):
The Serial Interface Enable and Load
Control. When CS/LD is low the CLK signal is enabled, so
the data can be clocked in. When CS/LD is pulled high,
data is loaded from the shift register into the DAC
register, updating the DAC output. When CS/LD is high
the CLK is disabled internally.
PI
FU
CTIO
N
S
U
U
D
OUT
(Pin 4):
The Output of the Shift Register Which
Becomes Valid on the Rising Edge of the Serial Clock.
GND (Pin 5):
Ground.
CLR (Pin 6):
The Clear Input. When pulled low, this pin
asynchronously clears the internal shift and DAC registers
to zero scale. Should be tied high for normal operation.
V
OUT
(Pin 7):
The Buffered DAC Output.
V
CC
(Pin 8):
The Positive Supply Input. 4.5V
V
CC
5.5V.
Requires a bypass capacitor to ground.
B11
MSB
B10
t
1
t
9
B1
t
6
B0
LSB
B11
CURRENT WORD
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1456 TD
B0
PREVIOUS WORD
B11
PREVIOUS WORD
B10
B1
B0
W
IAGRA
BLOCK
DAC
REGISTER
LD
12-BIT
SHIFT
REGISTER
POWER-ON
RESET
1146 BD
CLK 1
D
IN
2
D
OUT
4
V
OUT
7
CLR
6
GND
5
V
CC
8
3
CS/LD
12-BIT
DAC
2.048V
+
TW U
W
相關(guān)PDF資料
PDF描述
LTC1456C 12-Bit Rail-to-Rail Micropower DAC with Clear Input
LTC1456CN8 Low-Power LinCMOS(TM) Quad Comparator with Totem Pole Output 14-SOIC -55 to 125
LTC1456CS8 12-Bit Rail-to-Rail Micropower DAC with Clear Input
LTC1456I Low-Power LinCMOS(TM) Quad Comparator with Totem Pole Output 20-LCCC -55 to 125
LTC1456IS8 Low-Power LinCMOS(TM) Quad Comparator with Totem Pole Output 14-CDIP -55 to 125
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