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參數(shù)資料
| 型號： | LTC1472 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual General Purpose LinCMOS(TM) Differential Comparator 8-PDIP -40 to 85 |
| 中文描述： | 受保護(hù)的PCMCIA虛擬通道連接和VPP開關(guān)矩陣 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 300K |
| 代理商： | LTC1472 |
8
LTC1472
OPERATIO
V
CC
XOR Input Circuitry
The LTC1472 ensures that the 3.3V and 5V switches are
never turned on at the same time by employing an XOR
function which locks out the 3.3V switch when the 5V
switch is turned on, and locks out the 5V switch when the
3.3V switch is turned on. This XOR function also makes it
possible for the LTC1472 to work with either active-low or
active-high PCMCIA V
CC
switch control logic (see Applica-
tions Information for further details).
U
to ground. Both switches also have independent thermal
shutdown which limits the power dissipation to safe
levels.
V
CC
Break-Before-Make Switch Control
The LTC1472 has built-in delays to ensure that the 3.3V
and 5V switch are non-overlapping. Further, the gate
charge pumps include circuity which ramps the NMOS
switches on slowly (400
μ
s typical rise time) but turn off
much more quickly (typically 10
μ
s).
V
CC
Bias, Oscillator and Gate Charge Pump
When either the 3.3V or 5V switch is enabled, a bias
current generator and high frequency oscillator are turned
on. An on-chip capacitive charge pump generates ap-
proximately 12V of gate drive for the internal low R
DS(ON)
NMOS V
CC
switches from the 5V
IN
power supply. There-
fore, an external 12V supply is not required to switch the
V
CC
output. The 5V
IN
supply current drops below 1
μ
A
when both switches are turned off.
V
CC
Gate Charge and Discharge Control
Both V
CC
switches are designed to ramp on slowly (400
μ
s
typical rise time). Turn off time is much quicker
(typically 10
μ
s).
To ensure that both V
CC
NMOS switch gates are fully
discharged, program the switch to the high impedance
mode at least 100
μ
s before turning off the 5V
IN
power
supply.
V
CC
Switch Protection
Two levels of protection are designed into each of the
power switches in the LTC1472. Both V
CC
switches are
protected against accidental short circuits with SafeSlot
fold-back current limit circuits which limit the output
current to typically 1A when the V
CC(OUT)
output is shorted
THE VPP SWITCHING SECTION
The VPP switching section of the LTC1472 consists of the
following functional blocks:
VPP Switch Input TTL-CMOS Converters
The VPP inputs are designed to accommodate a wide
range of 3V and 5V logic families. The input threshold
voltage is 1.4V with
≈
100mV of hysteresis. The inputs
enable the bias generator, the gate charge pumps and the
protection circuitry. When the inputs are turned off, the
entire circuit is powered down and the V
DD
and VPP
IN
supply currents drop below 1
μ
A.
VPP Break-Before-Make Switch Control
The VPP input section has built-in delays to ensure that the
VPP switchs are non-overlapping. Further, the gate charge
pumps include circuitry which ramps the NMOS switches
on slowly but turns them off quickly.
VPP Bias, Oscillator and Gate Charge Pump
When either the VPP
IN
-VPP
OUT
or V
CC(IN)
-VPP
OUT
switch
is enabled, a bias current generator and high frequency
oscillator are turned on. An on-chip capacitive charge
pump generates approximately 23V of gate drive for the
internal low R
DS(ON)
NMOS VPP
IN
-VPP
OUT
switch from
the VPP
IN
power supply. The gate of the V
CC(IN)
-VPP
OUT
NMOS switch is either powered by the external 12V
regulator (if left on) or automatically from a built-in charge
pump powered from the V
DD
supply when the external 12V
supply drops below 10V. The V
DD
supply current drops
below 1
μ
A when switched to either the 0V or Hi-Z mode.
V
CC
EN0
0
1
0
1
V
CC
EN1
0
0
1
1
V
CC(OUT)
OFF
5V
3.3V
OFF
V
CC
Switch Truth Table
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