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參數(shù)資料
| 型號(hào)： | LTC1472CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Protected PCMCIA VCC and VPP Switching Matrix |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 300K |
| 代理商： | LTC1472CS |
11
LTC1472
APPLICATIO
S I
N
FOR
ATIO
U
Output Capacitors
The V
CC(OUT)
pin is designed to ramp on slowly, typically
400
μ
s rise time. Therefore, capacitors as large as 150
μ
F
can be driven without producing voltage spikes on the
5V
IN
or 3V
IN
supply pins (see graphs in Typical Perfor-
mance Characteristics). The V
CC(OUT)
pin should have a
0.1
μ
F to 1
μ
F capacitor for noise reduction and smoothing.
The VPP
OUT
pin should have a 0.01
μ
F to 0.1
μ
F capacitor
for noise reduction. The VPP
IN
capacitors should be at
least equal to the VPP
OUT
capacitors to ensure smooth
transitions between output voltages without creating spikes
on the system power supply lines.
W
U
Supply Sequencing
Because the 5V supply is the source of power for both the
V
CC
and VPP switch control logic, it is best to sequence the
power supplies such that the 5V supply is powered before
or simultaneous to the application of 3.3V or 12V power.
It is interesting to note however, that all of the switches in
the LTC1472 are NMOS transistors which require charge
pumps to generate gate voltages higher than the supply
rails for full enhancement. Because the gate voltages start
a 0V when the supplies are first activated, the switches
always start in the off state and do not produce glitches at
the output when powered.
Some PCMCIA switch matrix products employ PMOS
switches for 12V VPP control and great care must be taken
to ensure that the 5V control logic is powered before the
12V supply is turned on. If this sequence is not followed,
the PMOS VPP switch gate may start at ground potential
and the VPP output may be inadvertently forced to 12V.
Although, not advisable, it is possible to power the 12V
VPP
IN
supply pin of the LTC1472 prior to application of 5V
power. Only about 50
μ
A flows to the VPP
OUT
pin under
these conditions.
If the 5V supply must be turned off, it is important to
program all switches to the Hi-Z or 0V state at least 100
μ
s
before the 5V power is removed to ensure that all NMOS
switch gates are fully discharged to 0V.
Whenever possible however, it is best to leave the 5V
IN
and
V
DD
pins continuously powered. The LTC1472 quiescent
current drops to <1
μ
A with all the switches turned off and
therefore no 5V power is consumed in the standby mode.
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