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參數(shù)資料
| 型號： | LTC1478CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | Low-Power LinCMOS(TM) Dual Comparator 8-CDIP -55 to 125 |
| 中文描述： | 2.4 A BUF OR INV BASED PRPHL DRVR, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 224K |
| 代理商： | LTC1478CS |
6
LTC1477/LTC1478
APPLICATIO
S I
FOR
ATIO
U
ing of the switch parameters to the expected load current
and system current limit requirements.
A couple of examples are helpful:
1. If a nominal load of 1A was controlled by the switch
configured to current limit at 2A (all V
IN
pins connected
together), the R
DS(ON)
would be 0.07
and the voltage
drop across the switch would be 70mV. The power
dissipated by the switch would only be 70mW.
2. If a nominal load of 0.5A was controlled by the switch
configured to current limit at 0.85A (V
IN2
and V
IN3
disconnected), the R
DS(ON)
would increase to 0.14
.
But the voltage drop would remain at 70mV and the
switch power dissipation would drop to 35mW.
W
U
U
Supply Bypassing
For best results, bypass the supply input pins with a single
1.0
μ
F capacitor as close as possible to the LTC1477.
Sometimes, much larger capacitors are already available
at the output of the power supply. In this case, it is still
good practice to use a 0.1
μ
F capacitor as close as possible
to the LTC1477, especially if the power supply output
capacitor is more than 2 inches away on the printed circuit
board.
Output Capacitor
The output pin is designed to ramp on slowly, typically
1ms rise time. Therefore, very large output capacitors can
be driven without producing voltage spikes on the supply
pins (see graphs in Typical Performance Characteristics).
The output pin should have a 1
μ
F capacitor for noise
reduction and smoothing.
Supply and Input Sequencing
The LTC1477 is designed to operate with continuous
power (quiescent current drops to < 1
μ
A when disabled).
If the power must be turned off, for example to enter a
system “sleep” mode, the enable input must be turned off
100
μ
s before the input supply is turned off to ensure that
the gate of the NMOS switch is completely discharged
before power is removed. However, the input control and
power can be applied simultaneously during power up.
TYPICAL APPLICATIO
N
S
0.85A Protected Switch
2A Protected Switch Driving a Large Capacitive Load
+
C
LOAD
100
F
0.1
μ
F
LTC1477/1478 TA06
ON/OFF
2.7V TO 5.5V
LTC1477
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
V
OUT
+
1
μ
F
0.1
μ
F
LTC1477/1478 TA05
ON/OFF
2.7V TO 5.5V
I
SC
= 0.85A
NC
NC
LTC1477
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
+
1
μ
F
0.1
μ
F
LTC1477/1478 TA04
ON/OFF
2.7V TO 5.5V
I
SC
= 1.5A
NC
LTC1477
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
2A Protected Switch
1.5A Protected Switch
+
1
μ
F
0.1
μ
F
LTC1477/1478 TA03
ON/OFF
2.7V TO 5.5V
I
SC
= 2A
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
LTC1477
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