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參數(shù)資料
| 型號： | LTC1481IS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX RS485 SHTDN ULT LP 8SOIC |
| 標準包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
7
LTC1481
1481fa
Low Power Operation
The LTC1481 is designed to operate with a quiescent
current of 120
A max. With the driver in three-state, ICC
will drop to this 120
A level. With the driver enabled there
will be additional current drawn by the internal 12k resis-
tor. Under normal operating conditions this additional
current is overshadowed by the current drawn by the
Shutdown Mode
Both the receiver output (RO) and the driver outputs (A, B)
can be placed in three-state mode by bringing RE high and
DE low respectively. In addition, the LTC1481 will enter
shutdown mode when RE is high and DE is low.
In shutdown the LTC1481 typically draws only 1
A of
supply current. In order to guarantee that the part goes
into shutdown, DE must be low and RE must be high for
at least 600ns simultaneously. If this time duration is less
than 50ns the part will not enter shutdown mode. Toggling
either RE or DE will wake the LTC1481 back up within
3.5
s.
Propagation Delay
Many digital encoding schemes are dependent upon the
difference in the propagation delay times of the driver and
receiver. Figure 11 shows the test circuit for the LTC1481
propagation delay.
The receiver delay times are:
tPLH – tPHL = 13ns Typ, VCC = 5V
The drivers skew times are:
Skew = 5ns Typ, VCC = 5V
10ns Max, VCC = 5V, TA = – 40°C to 85°C
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
D
R
RECEIVER
OUT
R
54
100pF
TTL IN
tr, tf < 6ns
LTC1481 F11
Figure 11. Receiver Propagation Delay Test Circuit
LOGIC
VCC
SD3
P1
D1
OUTPUT
SD4
D2
N1
LTC1481 F09
ESD
LOGIC
VCC
P1
D1
OUTPUT
D2
N1
LTC1481 F10
Figure 9. LTC1481 Output Stage
Figure 10. Conventional CMOS Output Stage
The LTC1481 output stage will maintain a high impedance
state until the breakdown of the N-channel or P-channel is
reached when going positive or negative respectively. The
output will be clamped to either VCC or ground by a Zener
voltage plus a Schottky diode drop, but this voltage is well
beyond the RS485 operating range. Because the ESD
injected current in the N-well or substrate consists of
majority carriers, latch-up is prevented by careful layout
techniques. An ESD cell protects output against multiple
10kV human body model ESD strikes.
APPLICATIO S I FOR ATIO
WU
UU
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| LTC1482CMS8#TR | 功能描述:IC TXRX RS485 DET/FAILSAFE 8MSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:27 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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