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參數(shù)資料
| 型號(hào)： | LTC1482CN8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Quad General Purpose LinCMOS(TM) Differential Comparator 14-TSSOP |
| 中文描述： | LINE TRANSCEIVER, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大小： | 262K |
| 代理商： | LTC1482CN8 |
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9
LTC1482
FUU
Driver Enabled (DE = 1)
DI/SHDN
0
1
X
A
0
1
A Shorted to B
B
1
0
RO
0
1
1
CD
0
0
1
Driver Disabled (DE = 0, Notes 1, 2)
DI/SHDN
0
1
V
THCD(MIN)
< (A – B) < V
THCD(MAX)
1
A and B are Open
1
A and B are Shorted
1
V
THCD(MIN)
≥
(A – B)
≥
V
THCD(MAX)
and (A – B)
≤
V
THRO(MIN)
1
V
THCD(MIN)
≥
(A – B)
≥
V
THCD(MAX)
and (A – B)
≥
V
THRO(MAX)
X = Don’t Care
Z = High Impedance
A – B
X (Note 3)
RO
Z
1
1
1
0
CD
1 (Internal Pull-Up)
1
1
1
0
1
0
Note 1:
DE = 0, DI/SHDN = 0 puts the part in I
CC
shutdown and the supply
current drawn by the V
CC
pin drops to 20
μ
A max. The receiver is always
alive except in shutdown.
Note 2:
The table is valid regardless of the presence of an external
termination resistor.
Note 3:
Although the RO and the driver outputs are three-stated, the A and
B pins each present a 22k
receiver input resistance to ground.
TEST CIRCUITS
RECEIVER
OUTPUT
C
L
1k
S1
S2
TEST POINT
V
CC
1k
1482 F03
V
OD
A
B
R
R
V
OC
1482 F01
Figure 1. Driver DC Test Load #1
Figure 3. Receiver Timing Test Load
V
OD3
A
B
375
375
60
V
–7V TO 12V
1482 F02
Figure 2. Driver DC Test Load #2
Figure 5. Driver Timing Test Load
OUTPUT
UNDER TEST
C
L
S1
S2
V
CC
500
1482 F05
Figure 4. Driver/Receiver Timing Test Load
DE
A
B
DI
R
DIFF
V
CC
C
L1
C
L2
RO
CD
1k
15pF
A
B
1482 F04
(DE = 0, DI/SHDN = 0) or to disable the driver while keeping
the receiver alive (DE = 0, DI/SHDN = 1). When the driver
is enabled (DE = 1), DI/SHDN = 0 forces the A output low
and the B output high. DI/SHDN = 1 forces the A output
high and the B output low.
GND (Pin 5):
Ground.
A (Pin 6):
Driver Output/Receiver Input. The input resis-
tance is typically 22k when the driver is disabled (DE = 0).
When the driver is enabled, the A output follows the logic
level at the DI/SHDN pin.
B (Pin 7):
Driver Output/Receiver Input. The input resis-
tance is typically 22k when the driver is disabled (DE = 0).
When the driver is enabled, the B output is inverted from
the logic level at the DI/SHDN pin.
V
CC
(Pin 8):
Positive Supply. 4.75V < V
CC
< 5.25V. A 0.1
μ
F
bypass capacitor is recommended.
PI
FU
CTIO
N
S
U
U
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