tPHL RO –V
參數(shù)資料
型號: LTC1483IN8
廠商: Linear Technology
文件頁數(shù): 6/8頁
文件大?。?/td> 0K
描述: IC TXRX RS485 LOW EMI LOPWR 8DIP
標準包裝: 50
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應商設備封裝: 8-PDIP
包裝: 管件
6
LTC1483
sn1483 1483fs
SWITCHI G TI E WAVEFOR S
UW
W
1.5V
tPHL
RO
–VOD2
A – B
0V
1.5V
tPLH
OUTPUT
INPUT
VOD2
VOL
VOH
LTC1483 F07
tr ≤ 10ns, tf ≤ 10ns
Figure 7. Receiver Propagation Delays
1.5V
tZL(SHDN), tZL
tZH(SHDN), tZH
1.5V
tLZ
0.5V
tHZ
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
3V
0V
RE
5V
0V
RO
LTC1483 F08
tr ≤ 10ns, tf ≤ 10ns
Figure 8. Receiver Enable and Disable Times
APPLICATIO S I FOR ATIO
UU
W
U
Basic Theory of Operation
Traditionally RS485 transceivers have been designed us-
ing bipolar technology because the common-mode range
of the device must extend beyond the supplies and the
device must be immune to ESD damage and latch-up.
Unfortunately, most bipolar devices draw a large amount
of supply current, which is unacceptable for the numerous
applications that require low power consumption. The
LTC1483 is a CMOS RS485/RS422 transceiver which
features ultra-low power consumption without sacrificing
ESD and latch-up immunity.
The LTC1483 uses a proprietary driver output stage,
which allows a common-mode range that extends beyond
the power supplies while virtually eliminating latch-up and
providing excellent ESD protection. Figure 9 shows the
LTC1483 output stage while Figure 10 shows a conven-
tional CMOS output stage.
When the conventional CMOS output stage of Figure 10
enters a high impedance state, both the P-channel (P1)
and the N-channel (N1) are turned off. If the output is then
driven above VCC or below ground, the P+/N -well diode
(D1) or the N+/P-substrate diode (D2) respectively will
turn on and clamp the output to the supply. Thus, the
output stage is no longer in a high impedance state and is
not able to meet the RS485 common-mode range require-
ment. In addition, the large amount of current flowing
through either diode will induce the well-known CMOS
latch-up condition, which could destroy the device.
LOGIC
VCC
SD3
P1
D1
OUTPUT
SD4
D2
N1
LTC1483 F09
Figure 9. LTC1483 Output Stage
LOGIC
VCC
P1
D1
OUTPUT
D2
N1
LTC1483 F10
Figure 10. Conventional
CMOS Output Stage
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