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參數(shù)資料
| 型號： | LTC1531 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Self-Powered Isolated Comparator |
| 中文描述： | 自供電隔離比較 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 266K |
| 代理商： | LTC1531 |
7
LTC1531
APPLICATIO
S I
N
FOR
ATIO
U
W
U
tance, which will subsequently be discharged between
samples, will consume power from V
PW
.
ISOLATED COMPARATOR INPUTS AND CMPOUT
The LTC1531 isolated comparator has a 4-input
summing comparator that performs the following
comparison:
(V1 + V2)/2 > (V3 + V4)/2
By rearranging the equation, for example, a dual differen-
tial comparison is performed:
(V1 – V4) > (V3 – V2) or (V1 – V3) > (V4 – V2)
The input has a rail-to-rail input and common mode
voltage range of V
PW
-ISOGND. The summing nature of the
inputs allows midsupply referencing. For example, con-
necting V3 to V
REG
and V4 to ISOGND sums together to
provide V
REG
/2 for the negative comparator input. See for
example, the Isolated Switch Control.
Charge injection and leakage currents occur at the com-
parator inputs. The amount depends on how the compara-
tor is used. Minimum leakage currents occur with V1 = V2
and V3 = V4 where the input impedance is from charge
injection and is nominally 300M
. When V1
≠
V2 or
V3
≠
V4, the input impedance due to leakage currents is
about 15M
to 20M
. Since the comparator is turned on
only for the last 10
μ
s of the 108
μ
s V
REG
period, the charge
injection occurs at about the 98
μ
s point with a coupling
capacitance of 2pF per input.
The CMPOUT signal is typically used to provide hyster-
esis, as in the Isolated Temperature Control application.
CMPOUT is the latched result of the previous comparison
and is active during the following V
REG
ON period. CMPOUT
is powered by V
REG
, the internal 2.5V regulated output,
and is in high impedance except during the 108
μ
s
V
REG
ON time. When active, CMPOUT is switched low to
ISOGND or high to V
REG
depending on the stored result of
the previous comparison. The stored CMPOUT data is
reset during power-up. CMPOUT is not necessarily reset
by the powered side SHDN pin, except when shutdown
results in V
PW
drooping low enough to trigger a power-on
reset on the isolated side between 1.5V to 2.5V.
DATA, VALID, ZCDATA
During a power cycle, the VALID signal goes high if a valid
comparison was made during the previous listen cycle.
VALID goes low at the beginning of the next listen cycle.
The low-to-high transition of VALID can be used to clock
DATA into external circuitry. VALID is delayed 200ns after
the DATA output. In order for a comparison to occur,
sufficient power must be stored on the isolated side
storage capacitor.
The DATA output holds the last received compare result.
DATA is reset to zero on power-up and shutdown. The
VALID output is held high for one power cycle following a
correctly received compare result. The received DATA
value from the isolated side contains redundancy to im-
prove noise immunity.
The ZCDATA is a 25
μ
s output pulse triggered by the zero-
cross comparator. In order for a pulse to occur, the DATA
output must be at logic 1 and the ZCPOS-ZCNEG zero-
cross comparator input crosses 0V after the input has
exceeded the
±
150mV to 800mV of hysteresis. The zero-
cross comparator output is typically used to trigger a triac
from a 60Hz RC phase shifted AC line signal. See Typical
Applications.
Figure 5. V
REG
Output Stage
V
PW
V
REG
1531 F05
23k
16k
ISOGND
V
PW
V
GP
21k
2k
16k
1
ISOGND
1
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| LTC1531CSW | 功能描述:IC COMP ISOLATED SLF-PWRD 28SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LTC1531CSW#PBF | 功能描述:IC COMP ISOLATED SLF-PWRD 28SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LTC1531CSW#TR | 功能描述:IC COMP DIFF DUAL SELFPWR 28SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LTC1531CSW#TRPBF | 功能描述:IC COMP ISOLATED SLF-PWRD 28SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LTC1531IS8 | 制造商:Linear Technology 功能描述:Self-Powered Isolated Comparator |
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