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參數(shù)資料
| 型號： | LTC1535ISW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCEIVER RS485 ISO 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS485 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1354 (CN2011-ZH PDF) |
LTC1535
13
1535fb
APPLICATIONS INFORMATION
High Voltage Considerations
The LTC1535 eliminates ground loops on data commun-
ication lines. However, such isolation can bring potentially
dangerous voltages onto the circuit board. An example
would be accidental faulting to 117V AC at some point
on the cable which is then conducted to the PC board.
Figure 12 shows how to detect and warn the user or
installer that a voltage fault condition exists on the twisted
pair or its shield. A small (3.2mm) glow lamp is connected
between GND2 (the isolated ground) and the equipment’s
safety “earth” ground. If a potential of more than 75V
AC is present on the twisted pair or shield, B1 will light,
indicating a wiring fault. Resistors R3 and R4 are used
to ballast the current in B1. Two resistors are necessary
because they can only stand off 200V each, as well as for
power dissipation. As shown, the circuit can withstand a
direct fault to a 440V 3-phase system.
Other problems introduced by oating the twisted pair
include the collection of static charge on the twisted pair,
its shield and the attached circuitry. Resistors R1 and R2
provide a path to shunt static charge safely to ground.
Again, two resisitors are necessary to withstand high
voltage faults. Electrostatic spikes, electromagnetically
induced transients and radio frequency pickup are shunted
by addition capacitor C1.
Receiver Inputs Fail-Safe
The LTC1535 features an input common mode range
covering the entire RS485 specied range of –7V to 12V.
Differential signals of greater than ± 200mV within the
specied input common mode range will be converted
to TTL compatible signals at the receiver outputs, RO
and RO2. A small amount of input hyteresis is included
to minimize the effects of noise on the line signals. If
the receiver inputs are oating or shorted, a designed-in
receiver offset guarantees a fail-safe logic high at the
receiver outputs. If a fail-safe logic low is desired, connect
as shown in Figure 19.
TWISTED-PAIR
NETWORK
2
EQUIPMENT SAFETY GROUND
EARTH GROUND
2
FLOATING RS485 COMMON
*
IRC WCR1206
** IRC WCR1210
*** PANASONIC ECQ-U2A103MV
B1
CN2R (JKL)
1535 F12
R1*
470k
R2*
470k
R3**
100k
R4**
100k
C1***
10nF
2
Y
A
B
Z
GND2
LTC1535
Figure 12. Detecting Fault Conditions
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