參數(shù)資料
型號(hào): LTC1553L
廠商: Linear Technology Corporation
英文描述: 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor
中文描述: 5位可編程同步開關(guān)穩(wěn)壓器控制器的奔騰II處理器
文件頁數(shù): 11/20頁
文件大小: 370K
代理商: LTC1553L
11
LTC1553L
APPLICATIO
S I
FOR
ATIO
U
Soft Start and Current Limit
The LTC1553L includes a soft start circuit which is used
for initial start-up and during current limit operation. The
SS pin requires an external capacitor to GND with the value
determined by the required soft start time. An internal
11
μ
A current source is included to charge the external SS
capacitor. During start-up, the COMP pin is clamped to a
diode drop above the voltage at the SS pin. This prevents
the error amplifier, ERR, from forcing the loop to maxi-
mum duty cycle. The LTC1553L will begin to operate at low
duty cycle as the SS pin rises above about 1.2V (V
COMP
1.8V). As SS continues to rise, Q
SS
turns off and the error
amplifier begins to regulate the output. The MIN compara-
tor is disabled when soft start is active to prevent it from
overriding the soft start function.
The LTC1553L includes yet another feedback loop to
control operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
MOSFET, Q1, at the I
FB
pin. CC compares the voltage at I
FB
to the voltage at the I
MAX
pin. As the peak current rises, the
measured voltage across Q1 increases due to the drop
across the R
DS(ON)
of Q1. When the voltage at I
FB
drops
below I
MAX
, indicating that Q1’s drain current has ex-
ceeded the maximum level, CC starts to pull current out of
the external soft start capacitor, cutting the duty cycle and
controlling the output current level. The CC comparator
pulls current out of the SS pin in proportion to the voltage
difference between I
FB
and I
MAX
. Under minor overload
conditions, the SS pin will fall gradually, creating a time
delay before current limit takes effect. Very short, mild
overloads may not affect the output voltage at all. More
significant overload conditions will allow the SS pin to
reach a steady state, and the output will remain at a
reduced voltage until the overload is removed. Serious
overloads will generate a large overdrive at CC, allowing it
to pull SS down quickly and preventing damage to the
output components.
By using the R
DS(ON)
of Q1 to measure the output current,
the current limiting circuit eliminates an expensive dis-
crete sense resistor that would otherwise be required. This
W
U
U
helps minimize the number of components in the high
current path. Due to switching noise and variation of
R
DS(ON)
, the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuit begins to take effect will vary from unit to unit as the
R
DS(ON)
of Q1 varies.
For a given current limit level, the external resistor from
I
MAX
to V
IN
can be determined by:
=
(
R
I
R
I
IMAX
LMAX
DS O) 1
(
IMAX
)(
)
where,
I
I
I
LMAX
LOAD
RIPPLE
2
=
+
I
LOAD
= Maximum load current
I
RIPPLE
= Inductor ripple current
(
(
f
OSC
= LTC1553L oscillator frequency = 300kHz
L
O
= Inductor value
R
DS(ON)Q1
= Hot on-resistance of Q1 at I
LMAX
I
IMAX
= Internal 180
μ
A sink current at I
MAX
=
)(
)
)( )( )
V
V
V
f
L
V
IN
OUT
OUT
OSC
O
IN
Figure 5. Current Limit Setting
Q1
180
μ
A
G1
Q2
C
IN
L
O
V
OUT
1553L F05
C
OUT
R
IMAX
V
IN
+
CC
G2
20
LTC1553L
I
MAX
7
I
FB
8
+
+
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