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參數(shù)資料
| 型號： | LTC1555C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | SIM Power Supply and Level Translator |
| 中文描述： | SIM卡電源和電平轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 255K |
| 代理商： | LTC1555C |
9
LTC1555/LTC1556
I/O pin on the SIM side. The second method is to use the
DDRV pin to send data to the SIM and use the DATA pin to
receive data from the SIM. When the DDRV pin is not used,
it should either be left floating or tied to DV
CC
.
Level Translation with DV
CC
> V
CC
It is assumed that most applications for these parts will
use controller supply voltages (DV
CC
) less than or equal
to V
CC
. In cases where DV
CC
is greater than V
CC
by more
than 0.6V or so, the parts’ operation will be affected in the
following ways: 1) A small DC current (up to 100
μ
A) will
flow from DV
CC
to V
CC
through the DATA pull-up resistor,
N-channel pass device and the I/O pull-up resistor
(except when the part is in shutdown at which time DV
CC
is disconnected from V
CC
by turning off the pass device).
If the V
CC
load current is less than the DV
CC
current, the
V
CC
output may be pulled out of regulation until sufficient
load current pulls V
CC
back into regulation. 2) When the
SIM is sending data back to the controller, a logic high on
the I/O pin will result in the DATA pin being pulled up to
[V
CC
+ 1/3(DV
CC
– V
CC
)], not all the way up to DV
CC
. For
example, if DV
CC
is 5V and V
CC
is 3V, the DATA pin will
only swing from
≈
0.1V to 3.67V when receiving data
from the SIM side.
Optional LDO Output
The LTC1556 also contains an internal LDO regulator for
providing a low noise boosted supply voltage for low power
external circuitry (e.g., frequency synthesizers, etc.) Tying
the FB pin to the LDO pin provides a regulated 4.3V at the
LDO output (see Figure 4). A 3.3
μ
F (minimum) capacitor is
APPLICATIO
S I
FOR
ATIO
U
W
U
U
required to ensure output stability. A 10
μ
F low ESR capaci-
tor is recommended, however, to minimize LDO output
noise. The LDO output may also be used as an auxiliary
switch to V
CC
. If the FB pin is left floating or is tied to GND,
the LDO pin will be internally connected to the V
CC
output
through the P-channel pass device. The LDO may be dis-
abled at any time by switching the EN pin from DV
CC
to GND.
The 4.3V LDO output is usable only when V
CC
is 5V (or
greater). It is not available when V
CC
= 3V.
Figure 4. Auxiliary LDO Connections (LTC1556 Only)
V
REF
61k
V
CC
= 5V
1
μ
A
LDO
OFF ON
10
μ
F
TANT
4.3V
1555/56 F04
I
0mA to
10mA
FB153k
EN
–
+
+
10kV ESD Protection
All pins that connect to the SIM (CLK, RST, I/O, V
CC
, GND)
withstand over 10kV of human body model (100pF/1.5k
)
ESD. In order to ensure proper ESD protection, careful
board layout is required. The GND pins should be tied
directly to a GND plane. The V
CC
capacitor should be
located very close to the V
CC
pin and tied immediately to
the GND plane.
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