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參數(shù)資料
| 型號(hào)： | LTC1556CGN |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LEVEL TRANSLTOR W/LDO 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 55 |
| 邏輯功能： | 電平移位器 |
| 位數(shù)： | 1 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 傳輸延遲（最大）： | 18ns |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1355 (CN2011-ZH PDF) |
8
LTC1555/LTC1556
APPLICATIONS INFORMATION
WU
U
reduce the ripple. A larger COUT capacitor (22F or greater)
will reduce both the low and high frequency ripple due to
the lower COUT charging and discharging dV/dt and the
lower ESR typically found with higher value (larger case
size) capacitors. A low ESR ceramic output capacitor will
minimize the high frequency ripple, but will not reduce the
low frequency ripple unless a high capacitance value is
chosen (10
F or greater). A reasonable compromise is to
use a 10
Fto22Ftantalumcapacitorinparallelwitha1F
to 3.3
F ceramic capacitor on VOUT to reduce both the low
and high frequency ripple. An RC filter may also be used
to reduce high frequency voltage spikes (see Figure 1).
hundred milliseconds to completely shut down. To ensure
prompt and proper VCC shutdown, always force the M0
and M1 pins to a logic low state before shutting down the
DVCC supply (see Figure 2). Similarly, bring the DVCC
supply to a valid level before allowing the M0 and M1 pins
to go high when coming out of shutdown. This can be
achieved with pull-down resistors from M0 and M1 to
GND if necessary. (Note: shutting down the DVCC supply
with VIN active is not recommended with early date code
material. Consult factory for valid date code starting point
for shutting down the DVCC supply.)
Level Translators
All SIMs and smart cards contain a clock input, reset input
and a bidirectional data input/output. The LTC1555/
LTC1556 provide level translators to allow controllers to
communicate with the SIM (see Figures 3a and 3b). The
CLK and RST inputs to the SIM are level shifted from the
controller supply rails (DVCC and GND) to the SIM supply
rails (VCC and GND). The data input to the SIM may be
provided two different ways. The first method is to use the
DATA pin as a bidirectional level translator. This configu-
ration is only allowed if the controller data output pin is
open drain (all SIM I/O pins are open drain). Internal pull-
up resistors are provided for both the DATA pin and the
Figure 3b. Level Translator Connections for
One-Directional Controller Side DATA Flow
CIN
RIN
DATA
DDRV
DVCC
CLK
RST
I/O
VCC
CLK TO SIM
RST TO SIM
DATA FROM SIM
DATA TO SIM
LTC1555/LTC1556
CONTROLLER
SIDE
SIM SIDE
1555/56 F3b
Figure 3a. Level Translator Connections for
Bidirectional Controller DATA Pin
CIN
RIN
DATA
DDRV
DVCC
CLK
RST
I/O
VCC
CLK TO SIM
RST TO SIM
DATA TO/FROM SIM
LTC1555/LTC1556
CONTROLLER
SIDE
SIM SIDE
1555/56 F3a
Figure 2. Recommended DVCC Shutdown and Start-Up Timing
M0
DVCC
0V
M1
DVCC
0V
DVCC
0V
VCC
0V
1555/56 F02
Shutting Down the DVCC Supply
To conserve power, the DVCC supply may be shut down
while the VIN supply is still active. When the DVCC supply
is brought to 0V, weak internal currents will force the
LTC1555/LTC1556 into shutdown mode regardless of the
voltages present on the M0 and M1 pins. However, if the
M0 and M1 pins are floating or left connected to DVCC as
the supply is shut down, the parts may take several
Figure 1. VCC Output Ripple Reduction Techniques
15
F
TANTALUM
LT1555/56 F01
VCC
SIM
VCC
SIM
VCC
1
F
CERAMIC
10
F
VCC
10
F
2
LTC1555/
LTC1556
+
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