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參數(shù)資料
| 型號： | LTC1569CS8-6 |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER 10TH ORDR LOWPASS8SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 濾波器類型： | 線性相位，低通開關(guān)電容器 |
| 頻率 - 截止或中心： | 300kHz |
| 濾波器數(shù)： | 1 |
| 濾波器階數(shù)： | 10th |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
3
LTC1569-6
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VS = 3V (V + = 3V, V– = 0V), fCLK = 4.096MHz, fCUTOFF = 64kHz, RLOAD = 10k unless otherwise specified.
ELECTRICAL C
C
HARA TERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output DC Offset
REXT = 10k, Pin 5 Shorted to Pin 7
VS = 3V
±2
±5mV
(Note 2)
VS = 5V
±6
±12
mV
VS = ±5V
±15
mV
Output DC Offset
REXT = 10k, Pin 5 Shorted to Pin 7
VS = 3V
25
V/°C
Drift
VS = 5V
25
V/°C
VS = ±5V
75
V/°C
Clock Pin Logic Thresholds
VS = 3V
Min Logical “1”
2.7
V
when Clocked Externally
Max Logical “0”
0.5
V
VS = 5V
Min Logical “1”
4.0
V
Max Logical “0”
0.5
V
VS = ±5V
Min Logical “1”
4.0
V
Max Logical “0”
0.5
V
Power Supply Current
fCLK = 256kHz (40k from Pin 6 to Pin 7,
VS = 3V
3
4
mA
(Note 3)
Pin 5 Open,
÷ 4), fCUTOFF = 4kHz
q
5mA
VS = 5V
3.5
5
mA
q
6mA
VS = 10V
4.5
7
mA
q
8mA
fCLK = 4.096MHz (10k from Pin 6 to Pin 7,
VS = 3V
8
mA
Pin 5 Shorted to Pin 4,
÷ 1), fCUTOFF = 64kHz
q
11
mA
VS = 5V
9
mA
q
13
mA
VS = 10V
12
mA
q
17
mA
Clock Feedthrough
Pin 5 Open
0.1
mVRMS
Wideband Noise
Noise BW = DC to 2 fCUTOFF
95
VRMS
THD
fIN = 3kHz, 1.5VP-P, fCUTOFF = 32kHz
80
dB
Clock-to-Cutoff
64
Frequency Ratio
Max Clock Frequency
VS = 3V
5
MHz
(Note 4)
VS = 5V
5
MHz
VS = ±5V
7
MHz
Min Clock Frequency
VS = 3V, 5V, TA < 85°C
1.5
kHz
(Note 5)
VS = ±5V
3kHz
Input Frequency Range
Aliased Components <–65dB
0.9 fCLK
Hz
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: DC offset is measured with respect to Pin 3.
Note 3: If the internal oscillator is used as the clock source and the divide-
by-4 or divide-by-16 mode is enabled, the supply current is reduced as
much as 40% relative to the divide-by-1 mode.
Note 4: The maximum clock frequency is arbitrarily defined as the
frequency at which the filter AC response exhibits >1dB of gain peaking.
Note 5: The minimum clock frequency is arbitrarily defined as the frequecy
at which the filter DC offset changes by more than 5mV.
Note 6: For more details refer to the Input and Output Voltage Range
paragraph in the Applications Information section.
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