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參數(shù)資料
| 型號： | LTC1569CS8-7 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Linear Phase, DC Accurate, Tunable, 10th Order Lowpass Filter |
| 中文描述： | CONTINUOUS TIME FILTER, PIN OR RESISTOR PROGRAMMABLE, LOWPASS, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 217K |
| 代理商： | LTC1569CS8-7 |
4
LTC1569-6
TYPICAL PERFOR U
THD vs Input Voltage
THD vs Input Frequency
INPUT VOLTAGE (V
P-P
)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
T
1569-6 G02
–50
–55
–60
–65
–70
–75
–80
–85
–90
f
IN
= 3kHz
f
C+
= 32kHz
IN
TO OUT
V
S
= 5V
PIN 3 = 2V
V
S
= 3V
PIN 3 = 1.11V
INPUT FREQUENCY (kHz)
0
5
10
15
20
25
30
T
1569-6 G01
–60
–65
–70
–75
–80
–85
–90
V
IN
= 1.5V
P-P
f
C+
= 32kHz
IN
TO OUT
V
S
= 5V
PIN 3 = 2V
PI
FU
CTIO
N
S
U
U
IN
+
/IN
–
(Pins 1, 2):
Signals can be applied to either or
both input pins. The DC gain from IN
+
(Pin 1) to OUT
(Pin8) is 1.0, and the DC gain from Pin 2 to Pin 8 is –1. The
input range, input resistance and output range are de-
scribed in the Applications Information section. Input
voltages which exceed the power supply voltages should
be avoided. Transients will not cause latchup if the current
into/out of the input pins is limited to 20mA.
GND (Pin 3):
The GND pin is the reference voltage for the
filter and should be externally biased to 2V (1.11V) to
maximize the dynamic range of the filter in applications
using a single 5V (3V) supply. For single supply operation,
the GND pin should be bypassed with a quality 1
μ
F
ceramic capacitor to V
–
(Pin 4). The impedance of the
circuit biasing the GND pin should be less than 2k
as the
GND pin generates a small amount of AC and DC current.
For dual supply operation, connect Pin3 to a high quality
DC ground. A ground plane should be used. A poor ground
will increase DC offset, clock feedthrough, noise and
distortion.
V
–
/V
+
(Pins 4, 7):
For 3V, 5V and
±
5V applications a
quality 1
μ
F ceramic bypass capacitor is required from V
+
(Pin 7) to V
–
(Pin 4) to provide the transient energy for the
internal clock drivers. The bypass should be as close as
possible to the IC. In dual supply applications (Pin 3 is
grounded), an additional 0.1
μ
F bypass from V
+
(Pin 7) to
GND (Pin 3) and V
–
(Pin 4) to GND (Pin 3) is recom-
mended.
The maximum voltage difference between GND (Pin 3) and
V
+
(Pin 7) should not exceed 5.5V.
DIV/CLK (Pin 5):
DIV/CLK serves two functions. When the
internal oscillator is enabled, DIV/CLK can be used to
engage an internal divider. The internal divider is set to 1:1
when DIV/CLK is shorted to V
–
(Pin 4). The internal divider
is set to 4:1 when DIV/CLK is allowed to float (a 100pF
bypass to V
–
is recommended). The internal divider is set
to 16:1 when DIV/CLK is shorted to V
+
(Pin 7). In the
divide-by-4 and divide-by-16 modes the power supply
current is reduced by as much as 40%.
When the internal oscillator is disabled (R
X
shorted
to V
–
) DIV/CLK becomes an input pin for applying an
external clock signal. For proper filter operation, the clock
waveform should be a squarewave with a duty cycle as
close as possible to 50% and CMOS voltages levels (see
Electrical Characteristics section for voltage levels). DIV/
CLK pin voltages which exceed the power supply voltages
should be avoided. Transients will not cause latchup if the
fault current into/out of the DIV/CLK pin is limited to 40mA.
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