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參數(shù)資料
| 型號(hào)： | LTC1589IG#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC SOFTSPAN 14BIT 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | LTC275x 18-Bit DAC |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SoftSpan™ |
| 設(shè)置時(shí)間： | 2µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | * |
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4
LTC1588/LTC1589/LTC1592
1588992fa
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale
(LTC1592).
±1LSB = ±0.006% of full scale = ±61.2ppm of full scale
(LTC1589).
±1LSB = 0.024% of full scale = ±244.8ppm of full scale
(LTC1588).
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: IOUT1 with DAC register loaded to all 0s.
Note 6: Typical temperature coefficient is 100ppm/
°C.
Note 7: To 0.0015% for a full-scale change, measured from the falling
edge of LD for the LTC1592 only.
Note 8: REF = 6VRMS at 1kHz. DAC register loaded with all 1s. Output
amplifier = LT1468.
ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
VCC
Supply Voltage
q
4.5
5
5.5
V
ICC
Supply Current, VCC
Digital Inputs = 0V or VCC
q
10
A
Note 9: Calculation from en = √4kTRB where: k = Boltzmann constant
(1.38E-23 J/
°K); R = resistance (); T = temperature (°K); B = bandwidth
(Hz).
Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191
to 8192 for the LTC1589, 2047 to 2048 for the LTC1588.
Note 11: R1 and R2 are measured between R1 and RCOM, R2 and RCOM.
Note 12: If a continuous clock is used with data changing on the rising
edge of SCK, setup and hold time (t1, t2) will limit the maximum clock
frequency. If data changes on the falling edge of SCK then the setup time
will limit the maximum clock frequency to 8MHz (continuous 50% duty
cycle clock).
Note 13: SDO propagation delay and SDI setup time (t8, t1) limit the
maximum clock frequency for daisy chaining.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TIME (
s)
0
OUTPUT
VOLTAGE
(mV)
–10
0
10
0.6
1.0
1588992 G03
–20
–30
–40
0.2
0.4
0.8
20
30
40
USING AN LT1468
CFEEDBACK = 30pF
VREF = 10V
1nV-s TYPICAL
Midscale Glitch Impulse
(LTC1588/LTC1589/LTC1592)
Supply Current vs Input Voltage
INPUT VOLTAGE (V)
0
SUPPLY
CURRENT
(mA)
3
4
5
4
1588992 G09
2
1
0
1
2
3
5
VCC = 5V
ALL DIGITAL INPUTS
TIED TOGETHER
Logic Threshold vs Supply Voltage
SUPPLY VOLTAGE (V)
0
LOGIC
THRESHOLD
(V)
0.5
1.0
1.5
2.0
3.0
1
234
1588992 G10
57
6
2.5
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