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參數(shù)資料
| 型號： | LTC1590 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual Serial 12-Bit Multiplying DAC(雙路串行電流輸出12位乘法數(shù)模轉(zhuǎn)換器) |
| 中文描述： | 雙串行12位乘法DAC（雙路串行電流輸出12位乘法數(shù)模轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 247K |
| 代理商： | LTC1590 |
9
LTC1590
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Op Amp Selection
To maintain the excellent accuracy and stability of the
LTC1590 thought should be given to op amp selection.
Fortunately, the sensitivity of INL and DNL to op amp offset
has been significantly reduced compared to competing
parts of this type. The op amp’s V
OS
causes DAC output
offset. In addition, because the DAC’s equivalent output
resistance R
O
changes as a function of code, there is a
code-dependent DAC output error proportional to V
OS
. For
fixed reference applications this causes gain, INL and DNL
error. For multiplying applications, a code-dependent, DC
output voltage error is seen. At zero scale the DAC output
error is equal to the op amp offset, and at full scale the
output error is equal to twice the op amp offset. For
example, a 1mV op amp offset will cause a 0.41LSB zero-
scale error and a 0.82LSB full-scale error with a 10V full-
scale range. The offset caused INL error is approximately
0.4 times the op amp V
OS
and DNL error is 0.07 times op
amp V
OS
. For the same example of 1mV op amp V
OS
and
10V full-scale range, the INL degradation will be 0.17LSB
and DNL degradation will be 0.03LSB.
Op amp bias current causes only an offset error equal to
(I
BIAS
)(R
FB
)
≈
(I
BIAS
)(11k
). For example, a 100nA op
amp bias current causes a 1.1mV DAC offset, or 0.45LSB
for a 10V full-scale range. It is important to note that
connecting the op amp noninverting input to ground
through a resistor will not cancel bias current errors and
should never be done! Similarly an offset caused by op
amp bias current should not be adjusted by using the op
amp null pins since this increases offset between DAC
OUT1 and OUT2 pins, causing INL, DNL and gain errors.
If op amp offset error adjustment is required, the op amp
input offset voltage (the voltage difference between OUT1
and OUT2) should be nulled.
Grounding
As with any high precision data converter, clean ground-
ing is important. A low impedance analog ground plane
and star grounding should be used. OUT2 carries the
complementary DAC output current and should be tied to
the star ground with as low a resistance as possible. Other
ground points that must be tied to the star ground point
include the V
REF
input ground, the op amp noninverting
input(s) and the V
OUT
ground reference point.
13
14
11
12
15
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
CLEAR
16
9
8
1
2
10
1590 TA07
3
5
7
1
8
6
4
5
6
2
3
4
V
OUT B
V
OUT A
5V
V
±
10V
V
±
10V
7
33pF
0.1
μ
F
0.01
μ
F
33pF
15V
–15V
0.01
μ
F
V
OUT
= –V
IN
D
4096
(
)
DAC B
V
REF B
R
FB B
V
REF A
R
FB A
DAC A
24-BIT
SHIFT
REG
AND
LATCH
D
IN
CLK
CS/LD
D
OUT
CLR
DGND
AGND
LTC1590
OUT1 B
OUT2 B
OUT2 A
OUT1 A
+
–
+
–
1/2
LT1358
1/2
LT1358
TYPICAL APPLICATIO
N
S
Dual Programmable Attenuator
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