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參數(shù)資料
| 型號： | LTC1590IN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Dual Serial 12-Bit Multiplying DAC |
| 中文描述： | DUAL, SERIAL INPUT LOADING, 0.3 us SETTLING TIME, 12-BIT DAC, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 288K |
| 代理商： | LTC1590IN |
3
LTC1590
V
CC
= 4.5V to 5.5V, V
REF
= 10V, V
OUT1
= V
OUT2
= AGND = DGND = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
Analog Outputs
C
OUT
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Capacitance (Note 3)
DAC Register Loaded to All 1s
DAC Register Loaded to All 0s
G
G
60
30
90
60
pF
pF
Digital Input
V
IH
V
IL
I
IN
C
IN
Digital Output
V
OH
V
OL
Timing Characteristics
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Power Supply
V
CC
I
CC
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Input Capacitance
G
2.4
V
V
G
0.8
±
1
8
G
0.001
μ
A
pF
(Note 3) V
IN
= 0V
G
Digital Output High Voltage
Digital Output Low Voltage
I
OH
= 200
μ
A
I
OH
= 1.6mA
G
4
V
V
G
0.4
D
IN
to CLK Setup Time
D
IN
to CLK Setup Hold Time
CLK High Time
CLK Low Time
CS/LD High Time
LSB CLK to CS/LD
CS/LD Low to CLK High
CLK Low to CS/LD Low
CLK to D
OUT
Delay
G
50
0
40
40
50
40
20
20
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
G
G
G
G
G
G
G
G
160
Operating Supply Range
Supply Current
G
4.5
5
5.5
10
V
Digital Inputs = 0V or V
CC
G
μ
A
Note 8:
Glitch on DAC A or DAC B output when the other DAC makes a
full-scale transition.
Note 9:
10Hz to 100kHz. Calculation from e
n
=
√
4KTRB where:
K = Boltzmann constant (J/K
°
); R = resistance (
); T = resistor temperature
(
°
K); B = bandwidth (Hz).
Note10:
V
REF
= 6V
RMS
at 1kHz. DAC register loaded with all 1s, using
LT
1124 op amp.
Note 11:
V
REF
=
±
10V, 10kHz sine wave, DAC register loaded with all 0s,
using LT1358 op amp.
Note 12:
–3dB bandwidth using LT1358 op amp.
The
G
denotes specifications which apply over the full operating
temperature range.
Note 1:
±
0.5LSB =
±
0.012% of full scale.
Note 2:
Using internal feedback resistor.
Note 3:
Guaranteed by design, not subject to test.
Note 4:
I
OUT1
with DAC register loaded with all 0s.
Note 5:
OUT1 load = 100
in parallel with 13pF.
Note 6:
V
REF
= 0V. DAC register contents changed from all 0s to all 1s or
all 1s to all 0s.
Note 7:
DAC A output with V
REF A
= 0V and V
REF B
= 10kHz 20V
P-P
, or
DAC B output with V
REF B
= 0V, V
REF A
= 10kHz 20V
P-P
. Both DAC registers
loaded with all 1s.
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