APPLICATIONS IN
  • 參數(shù)資料
    型號: LTC1591CG#TR
    廠商: Linear Technology
    文件頁數(shù): 6/20頁
    文件大?。?/td> 0K
    描述: IC DAC 14BIT PARALLEL IN 28SSOP
    標(biāo)準(zhǔn)包裝: 2,000
    設(shè)置時(shí)間: 2µs
    位數(shù): 14
    數(shù)據(jù)接口: 并聯(lián)
    轉(zhuǎn)換器數(shù)目: 1
    電壓電源: 單電源
    功率耗散(最大): 55µW
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
    供應(yīng)商設(shè)備封裝: 28-SSOP
    包裝: 帶卷 (TR)
    輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
    采樣率(每秒): *
    14
    LTC1591/LTC1597
    15917fa
    APPLICATIONS INFORMATION
    WU
    U
    Figure 1b. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to – VREF
    Bipolar Mode
    (4-Quadrant Multiplying, VOUT = – VREF to VREF)
    The LTC1591/LTC1597 contain on chip all the 4-quadrant
    resistors necessary for bipolar operation. 4-quadrant
    multiplying operation can be achieved with a minimum of
    external components, a capacitor and a dual op amp, as
    shown in Figure 2. With a fixed 10V reference, the circuit
    shown gives a precision bipolar – 10V to 10V output
    swing.
    Op Amp Selection
    Because of the extremely high accuracy of the 14-/16-bit
    LTC1591/LTC1597, thought should be given to op amp
    selection in order to achieve the exceptional performance
    of which the part is capable. Fortunately, the sensitivity of
    INL and DNL to op amp offset has been greatly reduced
    compared to previous generations of multiplying DACs.
    Op amp offset will contribute mostly to output offset and
    gain and will have minimal effect on INL and DNL. For the
    LTC1597, a 500
    μVopampoffsetwillcauseabout0.55LSB
    INL degradation and 0.15LSB DNL degradation with a 10V
    full-scale range. The main effects of op amp offset will be
    a degradation of zero-scale error equal to the op amp
    offset, and a degradation of full-scale error equal to twice
    the op amp offset. For the LTC1597, the same 500
    μV op
    amp offset (2mV offset for LTC1591) will cause a 3.3LSB
    zero-scale error and a 6.5LSB full-scale error with a 10V
    full-scale range.
    Op amp input bias current (IBIAS) contributes only a zero-
    scale error equal to IBIAS(RFB/ROFS) = IBIAS(6k). For a
    thorough discussion of 16-bit DAC settling time and op
    amp selection, refer to Application Note 74, “
    Component
    and Measurement Advances Ensure 16-Bit DAC Settling
    Time.”
    Reference Input and Grounding
    For optimum performance the reference input of the
    LTC1597 should be driven by a source impedance of less
    than 1k
    Ω. However, these DACs have been designed to
    minimize source impedance effects. An 8k
    Ω source im-
    pedance degrades both INL and DNL by 0.2LSB.
    As with any high resolution converter, clean grounding is
    important. A low impedance analog ground plane and star
    grounding should be used. AGND must be tied to the star
    ground with as low a resistance as possible.
    VCC
    LTC1597
    RFB
    ROFS
    5V
    LD
    3
    2
    98
    28
    23
    7
    22
    R1
    RCOM
    1
    REF
    4
    5
    0.1
    μF
    6
    IOUT1
    33pF
    VOUT =
    0V TO
    –VREF
    1591/97 F01b
    AGND
    DGND
    WR
    10 TO 21,
    24 TO 27
    WR
    CLR
    VREF
    +
    LT1001
    16-BIT DAC
    R1
    R2
    16
    DATA
    INPUTS
    Unipolar Binary Code Table
    DIGITAL INPUT
    BINARY NUMBER
    IN DAC REGISTER
    –VREF (65,535/65,536)
    –VREF (32,768/65,536) = –VREF/2
    –VREF (1/65,536)
    0V
    LSB
    1111 1111
    1111
    0000 0000
    0000
    0000 0000
    0001
    0000 0000
    0000
    ANALOG OUTPUT
    VOUT
    MSB
    1111
    1000
    0000
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