參數(shù)資料
型號: LTC1595AIN8#PBF
廠商: Linear Technology
文件頁數(shù): 12/16頁
文件大?。?/td> 0K
描述: IC D/A CONV 16BIT MULTPLYNG 8DIP
標準包裝: 50
設(shè)置時間: 1µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): *
LTC1595/LTC1596/LTC1596-1
5
159561fb
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ±1LSB = ±0.0015% of full-scale = ±15.3ppm of full-scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: IOUT1 with DAC register loaded with all 0s.
Note 6: Typical temperature coefficient is 100ppm/°C.
Note 7: OUT1 load = 100Ω in parallel with 13pF.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±10%, VREF = 10V, VOUT1 = GND = 0V, TA = TMIN to TMAX, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1595)
tDS
Serial Input to CLK Setup Time
l
30
5
ns
tDH
Serial Input to CLK Hold Time
l
30
5
ns
tSRI
Serial Input Data Pulse Width
l
60
ns
tCH
Clock Pulse Width High
l
60
ns
tCL
Clock Pulse Width Low
l
60
ns
tLD
Load Pulse Width
l
60
ns
tASB
LSB Clocked into Input Register to DAC Register Load Time
l
0
ns
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1596/LTC1596-1)
tDS1
Serial Input to Strobe Setup Time
STB1 Used as the Strobe
l
30
5
ns
tDS2
STB2 Used as the Strobe
l
20
–5
ns
tDS3
STB3 Used as the Strobe
l
25
0
ns
tDS4
STB4 Used as the Strobe
l
20
–5
ns
tDH1
Serial Input to Strobe Hold Time
STB1 Used as the Strobe
l
30
5
ns
tDH2
STB2 Used as the Strobe
l
40
15
ns
tDH3
STB3 Used as the Strobe
l
35
10
ns
tDH4
STB4 Used as the Strobe
l
40
15
ns
tSRI
Serial Input Data Pulse Width
l
60
ns
tSTB1 to tSTB4
Strobe Pulse Width
(Note 11)
l
60
ns
tSTB1 to tSTB4
Strobe Pulse Width
(Note 12)
l
60
ns
tLD1, tLD2
LD Pulse Width
l
60
ns
tASB
LSB Strobed Into Input Register to Load DAC
Register Time
l
0
ns
tCLR
Clear Pulse Width
l
100
ns
tPD1
STB1 to SRO Propagation Delay
CL = 50pF
l
30
150
ns
tPD
STB2, STB3, STB4 to SRO Propagation Delay
CL = 50pF
l
30
200
ns
Power Supply
VDD
Supply Voltage
l
4.5
5
5.5
V
IDD
Supply Current
Digital Inputs = 0V or VDD
l
1.5
10
A
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD1, LD2 or LD.
Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s;
op amp = LT1007.
Note 10: Calculation from en = √4kTRB where: k = Boltzmann constant
(J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz).
Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time
for STB3.
Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.
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