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參數(shù)資料
| 型號： | LTC1597BIN |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 16BIT PAR 28-DIP |
| 標準包裝： | 14 |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 55µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | * |
13
LTC1591/LTC1597
15917fa
Description
The LTC1591/LTC1597 are 14-/16-bit multiplying, current
output DACs with a full parallel 14-/16-bit digital interface.
The devices operate from a single 5V supply and provide
both unipolar 0V to – 10V or 0V to 10V and bipolar
±10V
output ranges from a 10V or –10V reference input. They
have three additional precision resistors on chip for bipo-
lar operation. Refer to the block diagrams regarding the
following description.
The 14-/16-bit DACs consist of a precision R-2R ladder for
the 11/13LSBs. The 3MSBs are decoded into seven seg-
ments of resistor value R. Each of these segments and the
R-2R ladder carries an equally weighted current of one
eighth of full scale. The feedback resistor RFB and
4-quadrant resistor ROFS have a value of R/4. 4-quadrant
resistors R1 and R2 have a magnitude of R/4. R1 and R2
together with an external op amp (see Figure 2) inverts the
reference input voltage and applies it to the 14-/16-bit DAC
input REF, in 4-quadrant operation. The REF pin presents
a constant input impedance of R/8 in unipolar mode and
R/12 in bipolar mode. The output impedance of the current
output pin IOUT1 varies with DAC input code. The IOUT1
capacitance due to the NMOS current steering switches
also varies with input code from 70pF to 115pF. An added
feature of these devices, especially for waveform genera-
tion, is a proprietary deglitcher that reduces glitch energy
to below 2nV-s over the DAC output voltage range.
Digital Section
The LTC1591/LTC1597 are 14-/16-bit wide full parallel
data bus inputs. The devices are double-buffered with two
14-/16-bit registers. The double-buffered feature permits
the update of several DACs simultaneously. The input
register is loaded directly from a 16-bit microprocessor
bus when the WR pin is brought to a logic low level. The
second register (DAC register) is updated with the data
from the input register when the LD pin is brought to a
logic high level. Updating the DAC register updates the
DAC output with the new data. To make both registers
transparent for flowthrough mode, tie WR low and LD
high. However, this defeats the deglitcher operation and
output glitch impulse may increase. The deglitcher is
activated on the rising edge of the LD pin. The versatility
of the interface also allows the use of the input and DAC
registers in a master slave or edge-triggered configura-
tion. This mode of operation occurs when WR and LD are
tied together. The asynchronous clear pin resets the
LTC1591/LTC1597 to zero scale and the LTC1591-1/
LTC1597-1 to midscale. CLR resets both the input and
DAC registers. These devices also have a power-on reset.
Table 1 shows the truth table for the LTC1591/LT1597.
Unipolar Mode
(2-Quadrant Multiplying, VOUT = 0V to – VREF)
The LTC1591/LTC1597 can be used with a single op amp
to provide 2-quadrant multiplying operation as shown in
Figure 1. With a fixed – 10V reference, the circuits shown
give a precision unipolar 0V to 10V output swing.
APPLICATIONS INFORMATION
WU
U
Figure 1a. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to – VREF
VCC
LTC1591
RFB
ROFS
5V
LD
3
2
98
28
27
23
7
22
R1
RCOM
1
REF
4
5
0.1
μF
6
IOUT1
33pF
VOUT =
0V TO
–VREF
1591/97 F01a
AGND
DGND
WR
10 TO 21,
24, 25
WR
CLR
NC
CLR
VREF
–
+
LT1001
14-BIT DAC
R1
R2
14
DATA
INPUTS
Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
–VREF (16,383/16,384)
–VREF (8,192/16,384) = –VREF/2
–VREF (1/16,384)
0V
LSB
1111 1111
11
0000 0000
00
0000 0000
01
0000 0000
00
ANALOG OUTPUT
VOUT
MSB
1111
1000
0000
26
NC
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