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參數資料
| 型號： | LTC1604CG#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 16BIT SAMPLNG 36SSOP |
| 標準包裝： | 2,000 |
| 位數： | 16 |
| 采樣率（每秒）： | 333k |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 2 個單端，雙極；1 個差分，雙極 |
LTC1604
9
1604fa
APPLICATIONS INFORMATION
currents are shut down and only leakage current remains
(about 1μA). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47μF
capacitor.
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated,
it cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upset-
ting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <500ns), accuracy is unaffected.
Similarly, if CONVST returns high after the conversion is
over(e.g., CONVST low time >tCONV), accuracy is unaf-
fected. For best results, keep t5 less than 500ns or greater
than tCONV.
Figures 5 through 9 show several different modes of op-
eration. In modes 1a and 1b (Figures 5 and 6), CS and RD
are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are
t3
SHDN
CS
1604 F02a
t4
SHDN
CONVST
1604 F02b
t2
t1
CS
CONVST
RD
1604 F03
0
CHANGE
IN
DNL
(LSB)
2800
1604 F04
400
800
1600
1200
2000
2400
4
3
2
1
0
CONVST LOW TIME, t5 (ns)
tCONV
tACQ
Figure 2a. Nap Mode to Sleep Mode Timing
Figure 2b. SHDN to CONVST Wake-Up Timing
Figure 3. CS top CONVST Setup Timing
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
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