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參數(shù)資料
| 型號(hào)： | LTC1605-2CG |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 16BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，雙極 |
| 配用： | DC1255A-A-ND - BOARD SAR ADC LTC1605 |
10
LTC1605-1/LTC1605-2
APPLICATIONS INFORMATION
WU
U
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 7
s. No external adjustments
are required and, with the typical acquisition time of 1
s,
throughput performance of 100ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode, bring CS and
R/C low for no less than 40ns. Once initiated, it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low
while the conversion is in progress.
There are two modes of operation. The first mode is
shown in Figure 8. The digital input R/C is used to control
the start of conversion. CS is tied low. When R/C goes
low, the sample-and-hold goes into the hold mode and a
conversion is started. BUSY goes low and stays low
during the conversion and will go back high after the
conversion has been completed and the internal output
shift registers have been updated. R/C should remain low
for no less than 40ns. During the time R/C is low, the
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
t1
t11
t2
t 4
t3
t7
t6
ACQUIRE
CONVERT
ACQUIRE
t5
t8
tACQ
tCONV
t9
PREVIOUS
DATA VALID
PREVIOUS
DATA VALID
HI-Z
NOT VALID
HI-Z
DATA
VALID
DATA
VALID
R/C
BUSY
MODE
DATA MODE
1605-1/2 F08
digital outputs are in a Hi-Z state. R/C should be brought
back high within 3
s after the start of the conversion to
ensure that no errors occur in the digitized result. The
second mode, shown in Figure 9, uses the CS signal to
control the start of a conversion and the reading of the
digital output. In this mode, the R/C input signal should
be brought low no less than 10ns before the falling edge
of CS. The minimum pulse width for CS is 40ns. When CS
falls, BUSY goes low and will stay low until the end of the
conversion. BUSY will go high after the conversion has
been completed. The new data is valid when CS is
brought back low again to initiate a read. Again, it is
recommended that both R/C and CS return high within
3
s after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
straight binary for the LTC1605-1 and two’s complement
for the LTC1605-2. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low, the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
is taken high, the eight LSBs replace the eight MSBs
(Figure 10).
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