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參數(shù)資料
| 型號： | LTC1605CG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 16BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，雙極 |
| 配用： | DC1255A-A-ND - BOARD SAR ADC LTC1605 |
4
LTC1605
1605fc
LTC1605/LTC1605A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Positive Supply Voltage
(Notes 9, 10)
4.75
5.25
V
IDD
Positive Supply Current
●
11
16
mA
P
Power Dissipation
55
80
mW
LTC1605/LTC1605A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOL
Low Level Output Voltage
VDD = 4.75V
IO = 160A
0.05
V
IO = 1.6mA
●
0.10
0.4
V
IOZ
Hi-Z Output Leakage D15 to D0
VOUT = 0V to VDD, CS High
●
±10
A
COZ
Hi-Z Output Capacitance D15 to D0
CS High (Note 9)
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
UU
LTC1605/LTC1605A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
100
kHz
tCONV
Conversion Time
●
8
s
tACQ
Acquisition Time
●
2
s
t1
Convert Pulse Width
(Note 11)
●
40
ns
t2
Data Valid Delay After R/C
↓
(Note 9)
●
8
s
t3
BUSY Delay from R/C
↓
CL = 50pF
●
65
ns
t4
BUSY Low
8
s
t5
BUSY Delay After End of Conversion
220
ns
t6
Aperture Delay
40
ns
t7
Bus Relinquish Time
●
10
35
83
ns
t8
BUSY Delay After Data Valid
●
50
200
ns
t9
Previous Data Valid After R/C
↓
7.4
s
t10
R/C to CS Setup Time
(Notes 9, 10)
10
ns
t11
Time Between Conversions
10
s
t12
Bus Access and Byte Delay
(Notes 9, 10)
10
83
ns
TIMING CHARACTERISTICS
W
U
POWER REQUIREMENTS
W
U
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VANA =
VDIG = VDD, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above VDD
without latch-up.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a VIN input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
The
● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The
● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
The
● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
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