參數(shù)資料
型號: LTC1609CG#TRPBF
廠商: Linear Technology
文件頁數(shù): 7/24頁
文件大?。?/td> 0K
描述: IC CONV A/D 16BIT 200KSPS 28SSOP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 3 個(gè)單端,單極;3 個(gè)單端,雙極
15
LTC1609
1609fa
External Clock Mode
With the EXT/INT pin tied high, the DATACLK pin becomes
a digital input and the LTC1609 can accept an externally
supplied data clock. There are several ways in which the
conversion results can be clocked out. The data can be
clocked out during or after a conversion with a continuous
or discontinuous data clock. Figures 9 to 12 show the
timing diagram for each of these methods.
External Discontinuous Data Clock Data Read
After the Conversion
Figure 9 shows how the result from the current conver-
sion can be read out after the conversion has been
completed. The externally supplied data clock is running
discontinuously. R/C is used to initiate a conversion with
CS tied low. The conversion starts on the falling edge of
R/C. R/C should be returned high within 1.2
s to prevent
the transition from disturbing the conversion. After the
conversion has been completed (BUSY returning high), a
pulse on the SYNC pin will be generated on the rising edge
of DATACLK #0. The SYNC output can be captured on the
falling edge of DATACLK #0 or on the rising edge of
DATACLK #1. After the rising edge of DATACLK #1, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #1 or on the rising edge of DATACLK #2. The
LSB will be valid on the falling edge of DATACLK #16 or the
rising edge of DATACLK #17. After the rising edge of
DATACLK #17 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #1.
A minimum of 17 clock pulses are required if the data is
captured on falling clock edges.
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will
not degrade the 200kHz throughput. This method mini-
mizes the possible external disturbances that can occur
while a conversion is in progress and will yield the best
performance.
APPLICATIO S I FOR ATIO
WU
UU
Figure 9. Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/INT Tied High, CS Tied Low). Read Conversion Result After the Conversion
012
3
15
16
17
TAG0
TAG
DATA
SYNC
BUSY
R/C
EXTERNAL
DATACLK
TAG1
TAG2
TAG3
TAG15
B1
B14
B13
B15
(MSB)
B0
TAG0
TAG1
TAG2
TAG16
TAG17
TAG18
TAG19
1606 F09
t23
t24
t18
t17
t3
t2
t21
t1
t13
t14
t12
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